Visible to Intel only — GUID: lmx1685574898162
Ixiasoft
Visible to Intel only — GUID: lmx1685574898162
Ixiasoft
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings
Each byte and pin pair combination must be unique in the LVDS SERDES interface across receivers and transmitters. The combination of the channel byte and pins, and which I/O lane you place the channel byte, determines the pins locations within the I/O bank.
If you want to customize the pin selections, Altera recommends that you first plan your LVDS SERDES interface channels placement before configuring the Pin Settings tab. Refer to the related information.
Parameter | Value | Description |
---|---|---|
Customize Pin Selections |
|
Default is Off. |
Parameter | Value | Description |
---|---|---|
RX channel n byte | 00 to 07 | Select the byte reference to use for the RX channel. Use the Quartus® Prime Interface Planner tool to place the byte in an I/O lane. Refer to the related information for differential pin placement restrictions. |
RX channel n pin |
|
Select the pin pair reference within the byte. Refer to the related information for which pin pair to select based on which pin index numbers and I/O lane you want to place the channel. |
Parameter | Value | Description |
---|---|---|
TX outclock channel byte | 00 to 07 | Select the byte reference to use for the TX outclock. Use the Quartus® Prime Interface Planner tool to place the byte in an I/O lane. Refer to the related information for differential pin placement restrictions. |
TX outclock channel pin |
|
Select the TX outclock pin pair reference within the byte. Refer to the related information for which pin pair to select based on which pin index numbers and I/O lane you want to place the TX outclock. |
TX channel n byte | 00 to 07 | Select the byte reference to use for the TX channel. Use the Quartus® Prime Interface Planner tool to place the byte in an I/O lane. Refer to the related information for differential pin placement restrictions. |
TX channel n pin |
|
Select the pin pair reference within the byte. Refer to the related information for which pin pair to select based on which pin index numbers and I/O lane you want to place the channel. |