LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

ID 813929
Date 10/07/2024
Public
Document Table of Contents

11. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

Document Version Quartus® Prime Version Changes
2024.10.07 24.2 Added new topic: LVDS SERDES Intel® FPGA IP Transmitter Settings.
2024.07.08 24.2
  • Updated the table: Signal Interface between IOPLL and LVDS SERDES IPs.
    • Changed ext_vcoph[7:0] to ext_phout[7:0].
    • Added new signal phout_periph.
  • Updated the tables in topic: IOPLL Parameter Values for External PLL Mode.
    • Changed the parameters value for outclk1.
    • Added VCO Frequency output clock.
    • Removed outclk3 and outclk4.
    • Added new table: Generating Output Clocks Using an IOPLL IP for Transmitter Channel.
  • Updated the figures in topic Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode. Added ext_phout_periph signal in LVDS SERDES Receiver and phout_periph signal in IOPLL Intel® FPGA IP.
2024.04.08 24.1 Initial release.