LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

ID 813929
Date 7/08/2024
Public
Document Table of Contents

4.1. LVDS SERDES Receiver Blocks

The True Differential Signaling buffers can interface with LVDS, mini-LVDS, RSDS, and LVPECL compatible signaling. You can statically set the I/O standard of the receiver pins to True Differential Signaling in the Quartus® Prime Assignment Editor, Pin Planner, or .qsf file.
Figure 7. Receiver Block DiagramThis figure shows the hardware blocks of the receiver. In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively. The deserializer includes shift registers and parallel load registers, and sends a maximum of 8 bits to the internal logic.


Note: You do not need a PLL if you bypass the deserializer