LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

ID 813929
Date 7/08/2024
Public
Document Table of Contents

5.1. LVDS SERDES Intel® FPGA IP

The LVDS SERDES IP configures the serializer/deserializer (SERDES) and dynamic phase alignment (DPA) blocks. The IP also supports LVDS SERDES channel placements, legality checks, and LVDS SERDES channel-related rule checks.