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1. Agilex™ 5 LVDS SERDES Overview
2. Agilex™ 5 LVDS SERDES Architecture
3. Agilex™ 5 LVDS SERDES Transmitter
4. Agilex™ 5 LVDS SERDES Receiver
5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide
6. Agilex™ 5 LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 5 LVDS SERDES Design Guidelines
9. Agilex™ 5 LVDS SERDES Troubleshooting Guidelines
10. LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs Archives
11. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings
5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings
5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings
5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings
5.1.6.6. LVDS SERDES Intel® FPGA IP Clock Resource Summary
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS SERDES Transmitters and Receivers with External PLL
8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
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6.2.2. Receiver Skew Margin
Different modes of SERDES receivers use different specifications, which determine the ability to sample the received serial data correctly.
- In the non-DPA mode, use RSKM, TCCS, and sampling window (SW) specifications for high-speed source-synchronous differential signals in the receiver data path.
- In the DPA and Soft-CDR modes, use DPA jitter tolerance instead of the receiver skew margin (RSKM).
Equation 2. RSKM EquationThis equation expresses the relationship between RSKM, TCCS, and SW.
Symbol | Description |
---|---|
RSKM | The timing margin between the clock input of the receiver and the data input sampling window, and the jitter induced from core noise and I/O switching noise. |
Time unit interval (TUI) | The time period of the serial data. |
SW | The period of time that the input data must be stable to ensure that the LVDS SERDES receiver samples the data successfully. The SW is a device property and varies according to device speed grade. |
TCCS | The timing difference between the fastest and the slowest output edges across channels driven by the same PLL. The TCCS measurement includes the tCO variation, clock, and clock skew. |
Note: If there is additional board channel-to-channel skew, consider the total receiver channel-to-channel skew (RCCS) instead of TCCS. .
You must calculate the RSKM value, based on the data rate and device, to determine if the LVDS SERDES receiver can sample the data:
- A positive RSKM value, after deducting transmitter jitter, indicates that the LVDS SERDES receiver can sample the data properly.
- A negative RSKM value, after deducting transmitter jitter, indicates that the LVDS SERDES receiver cannot sample the data properly.
Figure 34. Differential High-Speed Timing Diagram and Timing Budget
RSKM Calculation Example
This example shows the RSKM calculation for Agilex™ 5 devices at 1 Gbps data rate with a 200 ps board channel-to-channel skew.
Equation 3. RSKM Calculation
The non-DPA receiver works correctly if the RSKM is greater than 0 ps after deducting transmitter jitter.