LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

ID 813929
Date 10/07/2024
Public
Document Table of Contents

8.3.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank

If you use true differential I/O standards and single-ended I/O standards in the same or adjacent HSIO banks, adhere to the following placement guidelines.
  • Do not place true differential and toggling single-ended I/O standards in the combinations of locations listed in the following tables.
  • The Quartus® Prime software issues the following errors:
    • Compilation error—violation of the same bank placement restriction.
    • Critical warning—assignment of true differential I/O standards to pin pairs with the following pin index numbers: 0 and 1, 6 and 7, 88 and 89, and 94 and 95.
Table 38.  Restricted Pin Placement Combinations for True Differential and Single-Ended I/O Standards in the Same HSIO Bank

This table lists the combinations of pins and I/O standards not allowed in the same HSIO bank. Examples:

  • If you place a true differential I/O standard in pin pair 10 and 11, do not place single-ended I/O standards in pins 8 or 19.
  • If you place a single-ended I/O standard in pin 57 or 67, do not place a true differential I/O standard in pin pair 58 and 59.
Combinations Not Allowed (Pin Index Number) Combinations Not Allowed (Pin Index Number) Combinations Not Allowed (Pin Index Number) Combinations Not Allowed (Pin Index Number)
True Differential Pin Pair Single-Ended Pin True Differential Pin Pair Single-Ended Pin True Differential Pin Pair Single-Ended Pin True Differential Pin Pair Single-Ended Pin
0 and 1 3, 4 24 and 25 27, 28 48 and 49 51, 52 72 and 73 75, 76
2 and 3 0 26 and 27 16, 24 50 and 51 40, 48 74 and 75 64, 72
4 and 5 1, 15 28 and 29 25, 39 52 and 53 49, 63 76 and 77 73, 87
6 and 7 9 30 and 31 22, 32 54 and 55 46, 56 78 and 79 70, 80
8 and 9 6, 11 32 and 33 31, 34 56 and 57 55, 58 80 and 81 79, 82
10 and 11 8, 19 34 and 35 33, 43 58 and 59 57, 67 82 and 83 81, 90
12 and 13 14, 17 36 and 37 38, 41 60 and 61 62, 65 84 and 85 86, 89
14 and 15 5, 12 38 and 39 29, 36 62 and 63 53, 60 86 and 87 77, 84
16 and 17 13, 26 40 and 41 37, 50 64 and 65 61, 74 88 and 89 85
18 and 19 10, 21 42 and 43 35, 45 66 and 67 59, 69 90 and 91 83, 92
20 and 21 18, 23 44 and 45 42, 47 68 and 69 66, 71 92 and 93 91, 94
22 and 23 20, 30 46 and 47 44, 54 70 and 71 68, 78 94 and 95 93
Table 39.  Restricted Pin Placement Combinations for True Differential and Single-Ended I/O Standards in Adjacent HSIO Banks

This table lists the combinations of pins and I/O standards not allowed in adjacent HSIO banks. Examples:

  • If you place a true differential I/O standard in pin pair 6 and 7 of bank 3B, do not place single-ended I/O standards in pin 95 of bank 3A.
  • If you place a single-ended I/O standard in pin 2 of bank 2B, do not place a true differential I/O standard in pin pair 88 and 89 of bank 2A.
Combinations Not Allowed (Pin Index Number) Combinations Not Allowed (Pin Index Number)
True Differential Single-Ended True Differential Single-Ended
Bank Pin Pair Bank Pin Bank Pin Pair Bank Pin
3A 88 and 89 3B 2 2A 88 and 89 2B 2
94 and 95 7 94 and 95 7
3B 2 and 3 3A 88 2B 2 and 3 2A 88
6 and 7 95 6 and 7 95

Refer to the related information for the figure showing the locations of the HSIO banks.