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1. Agilex™ 5 LVDS SERDES Overview
2. Agilex™ 5 LVDS SERDES Architecture
3. Agilex™ 5 LVDS SERDES Transmitter
4. Agilex™ 5 LVDS SERDES Receiver
5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide
6. Agilex™ 5 LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 5 LVDS SERDES Design Guidelines
9. Agilex™ 5 LVDS SERDES Troubleshooting Guidelines
10. LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs Archives
11. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings
5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings
5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings
5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings
5.1.6.6. LVDS SERDES Intel® FPGA IP Clock Resource Summary
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS SERDES Transmitters and Receivers with External PLL
8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
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4. Agilex™ 5 LVDS SERDES Receiver
The Agilex™ 5 LVDS SERDES receivers are dedicated circuitries.
Dedicated Circuitry / Feature | Description |
---|---|
Differential I/O buffer | Supports I/O standards compatible with LVDS, RSDS, SLVS, Mini-LVDS, and LVPECL:
|
Phase-locked loops (PLLs) | Generates different phases of a clock for data synchronizer |
Data realignment (bit slip) | Inserts bit latencies into serial data |
Dynamic phase alignment (DPA) | Chooses a phase closest to the phase of the serial data |
Synchronizer (FIFO buffer) | Compensate for phase differences between the data and the receiver’s input reference clock |
On-chip termination (OCT) | 100 Ω in True Differential Signaling I/O standards |