Visible to Intel only — GUID: sam1412833642936
Ixiasoft
Visible to Intel only — GUID: sam1412833642936
Ixiasoft
6.1. LVDS SERDES Intel® FPGA IP Timing
Timing Component | Description |
---|---|
Source Synchronous Paths | The source synchronous paths are paths where clock and data signals are passed from the transmitting devices to the receiving devices. For example:
|
Dynamic Phase Alignment Paths | A DPA block registers the I/O capture paths in soft-CDR and DPA-FIFO modes. The DPA block dynamically chooses the best phase from the PLL VCO clocks to latch the input data. |
Internal FPGA Paths | The internal FPGA paths are the paths inside the FPGA fabric:
The Timing Analyzer reports the corresponding timing margins. |
File Name | Description |
---|---|
<variation_name>_intel_lvds_core10_ph2_191_<random_id>.sdc |
This .sdc file allows the Quartus® Prime Fitter to optimize timing margins with timing-driven compilation. The file also allows the Timing Analyzer to analyze the timing of your design. The IP uses the .sdc for the following operations:
You can locate this file in the .qip generated during IP generation. |
sdc_util.tcl | This .tcl file is a library of functions and procedures that the .sdc uses. |