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1. Agilex™ 5 LVDS SERDES Overview
2. Agilex™ 5 LVDS SERDES Architecture
3. Agilex™ 5 LVDS SERDES Transmitter
4. Agilex™ 5 LVDS SERDES Receiver
5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide
6. Agilex™ 5 LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 5 LVDS SERDES Design Guidelines
9. Agilex™ 5 LVDS SERDES Troubleshooting Guidelines
10. LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs Archives
11. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings
5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings
5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings
5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings
5.1.6.6. LVDS SERDES Intel® FPGA IP Clock Resource Summary
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS SERDES Transmitters and Receivers with External PLL
8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
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5.1.6.2.3. Locating the I/O Lane and Channel Pin through the Interface Planner
After you have assigned the channel byte to an I/O lane, you can refer to information in the Interface Planner to verify the I/O lane number and pin index numbers.
- Select the channel byte design element (already placed) under the Design section.
- Refer to the Device Location > resources field in the Info tab under the Info section.
The number in the byte resource corresponds to the I/O lane number shown in the Pin Planner. For example, if the resource is BYTE-3, this corresponds to I/O Lane 3.
- To determine the I/O pins of the LVDS SERDES channels and the respective I/O bank:
- Clear the Design Element Filter box under the Design section.
- Switch to the Link Info tab.
- Click the hyperlink for the channel in the Fanin > IO_CLUSTER category.
For example, to verify the pins for receiver channel 0, click rx_in_p[0]~CLUSTER.The list under the Design section selects the design channel design element.
- Clear the Filter box under the Legal Locations section.
- Right-click the selected design element row and select Generate Legal Locations for Selected Element.
The Legal Locations section displays the differential pin pair.
- Right-click the differential pin pair in the Legal Locations section and select Zoom to Selected.
The chip view zooms to the pin pair and highlight them.
- Hover your mouse cursor at the edge of the selected I/O pad to view the bank and pin names.
- Click at the edge of the selected I/O pad to display the resource property under the Info section.
The Device Location > resources category displays the pad number that corresponds to the pin index number as shown in the Pin Planner and pin out files.
Figure 27. Interface Planner Showing the Bank Name, Pin Name, and Pin Index Number
You can compare how the assigned pins correspond to your channel selection in the Pin Settings tab of the LVDS SERDES IP parameter editor. For example, if you selected pin pair "0203" as the channel for byte 0, and then placed byte 0 to I/O lane 3 of bank 3A_B, the pins assigned to the channel has the index numbers as listed in Channel Pin in the Pin Settings Tab for Each HSIO Bank Pin Index Number Pair.