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1. Agilex™ 5 LVDS SERDES Overview
2. Agilex™ 5 LVDS SERDES Architecture
3. Agilex™ 5 LVDS SERDES Transmitter
4. Agilex™ 5 LVDS SERDES Receiver
5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide
6. Agilex™ 5 LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 5 LVDS SERDES Design Guidelines
9. Agilex™ 5 LVDS SERDES Troubleshooting Guidelines
10. LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs Archives
11. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings
5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings
5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings
5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings
5.1.6.6. LVDS SERDES Intel® FPGA IP Clock Resource Summary
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS SERDES Transmitters and Receivers with External PLL
8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
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5.1.6.2.2. Placing Channel Bytes in I/O Lanes
Use the Quartus® Prime Interface Planner to place the channel bytes in I/O lanes. Alternatively, you can use the .qsf file to assign the channel bytes to I/O lanes. The placement of the bytes determine the channel pins locations.
Before you begin:
- Optionally, plan your LVDS SERDES interface and note the full pin name and coordinate of one pin from each I/O lane. Refer to the related information.
- Set up the Pin Settings tab.
- Run Analysis & Synthesis for your project.
In the following steps, you use the pin name and coordinate to determine the I/O lane of the pin in the Interface Planner window and place the channel byte to the I/O lane.
- Open and initialize the Quartus® Prime Interface Planner.
- From the Quartus® Prime menu, select Tools > Interface Planner.
The Interface Planner window displays.
- From the Interface Planner menu, select Plan > Initialize Interface Planner. Wait for the initialization to complete.
- From the Interface Planner menu, select Plan > Update Plan.
The Assignments Applied window appears.
- Click OK.
- From the Quartus® Prime menu, select Tools > Interface Planner.
- Switch to the Plan tab.
- Find the byte elements of your LVDS SERDES IP.
- In Design Element Filter box, enter byte_0.
- Expand your LVDS SERDES IP instance under the Design Element column.
The Design section lists design elements that corresponds to the channel bytes you selected in the Pin Settings tab of the LVDS SERDES IP parameter editor.Figure 26. Interface Planner Listing the Channel Bytes Instances
- Right click a byte element and select Generate Legal Locations for Selected Element.
The Legal Locations window displays.
- Find the I/O lane of the pins you plan for your LVDS SERDES channels.
- Refer to the pin full name and coordinate you noted when planning the LVDS SERDES interface.
Alternatively, you can zoom in to the HSIO bank you want in the Interface Planner Chip View and look for the pin name. Once you select the pin, the Device Location > gid name field under the Info section of the Interface Planner displays the full pin name.
- In the Filter box under Legal Locations, enter the coordinate of the pin to make it easier to find your I/O lane.
For example, the pin full name is "IOPAD_X61_Y147_N330". Enter X61_Y147.
- From the filtered list, select the I/O lane with the closest number lower than the number in the last section of the pin full name.
For example, the number in the last section of the pin full name is "330". In the filtered list, select BYTE_X61_Y147_N309.
- Refer to the pin full name and coordinate you noted when planning the LVDS SERDES interface.
- Right-click the selected legal location and select Place at Selected.
The Placement column for selected row under the Design section updates with the selected resource.
You can verify the I/O lane and channel pins placement by using the Interface Planner to locate the I/O lane number and pin index number (as shown in the Pin Planner).