Visible to Intel only — GUID: sam1447676575843
Ixiasoft
Visible to Intel only — GUID: sam1447676575843
Ixiasoft
7.2. LVDS SERDES IP Simulation Design Example
Using the design example, you can run a simulation using a single command, depending on the simulator that you use. The simulation demonstrates how you can use the LVDS SERDES IP.
Generating and Using the Design Example
To generate the simulation design example from the source files for a Verilog simulator, run the following command in the design example directory:
quartus_sh -t make_sim_design.tcl VERILOGTo generate the simulation design example from the source files for a VHDL simulator, run the following command in the design example directory:
quartus_sh -t make_sim_design.tcl VHDLThe TCL script creates a sim directory that contains subdirectories—one for each supported simulation tool. You can find the scripts for each simulation tool in the corresponding directories.