Visible to Intel only — GUID: sam1412833606516
Ixiasoft
Visible to Intel only — GUID: sam1412833606516
Ixiasoft
5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings
Parameter | Value | Description |
---|---|---|
Enable bitslip mode |
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Turn on to add a bit slip block to the receiver data path and expose the rx_bitslip_ctrl port (one input per channel). Default is Off. Every assertion of the rx_bitslip_ctrl signal adds one bit of serial latency to the data path of the specified channel.
Note: You must enable this parameter for the IP simulation driver to function correctly.
|
Enable rx_bitslip_reset port |
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Turn on to expose the rx_bitslip_reset port (one input per channel) that you can use to reset the bit slip. Default is Off. This setting is available if you turn on Enable bitslip mode. |
Enable rx_bitslip_max port |
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Turn on to expose the rx_bitslip_max port (one output per channel). Default is Off. When asserted, the next rising edge of rx_bitslip_ctrl resets the latency of the bit slip to zero. This setting is available if you turn on Enable bitslip mode. |
Parameter | Value | Description |
---|---|---|
Enable rx_dpa_reset port |
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Turn on to expose the rx_dpa_reset port that you can use to reset the DPA logic of each channel independently. (Formerly known as rx_reset.) Default is Off. This setting is available if you select RX DPA-FIFO or RX Soft-CDR in RX functional mode. |
Enable rx_fifo_reset port |
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Turn on to use your logic to drive the rx_fifo_reset port to reset the DPA-FIFO block. Default is Off. This setting is available if you select RX DPA-FIFO in RX functional mode. |
Enable rx_dpa_hold port |
|
Turn on to expose the rx_dpa_hold input port (one input per channel). If set high, the DPA logic in the corresponding channel does not switch sampling phases. (Formerly known as rx_dpll_hold.) Default is Off. This setting is available if you select RX DPA-FIFO in RX functional mode. |
Parameter | Value | Description |
---|---|---|
Desired receiver inclock phase shift (degrees) | — | Specifies, in degrees of the LVDS fast clock, the ideal phase delay of inclock with respect to transitions in the incoming serial data. For example, specifying 180° implies that the inclock is center aligned to the incoming data. |
Actual receiver inclock phase shift (degrees) | Depends on the fast_clock and inclock frequencies. Refer to the related information. |
Specifies the closest achievable receiver inclock phase shift to the desired receiver inclock phase shift. |
RCCS (ps) | — | Specifies the RCCS value in picoseconds. Depending on the order the Quartus® Prime software reads the project .sdc files, this value may override any RCCS value you specify in the .sdc file. To avoid uncertainty, Altera recommends that you specify the RCCS value in only one of the locations. |