LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

ID 813929
Date 10/07/2024
Public
Document Table of Contents

5.1.3. LVDS SERDES IP Usage Modes

You can implement four usage modes using the LVDS SERDES IP.
  • Transmitter—specify the Number of TX channels to generate the IP as a transmitter.
  • Non-DPA receiver—specify the Number of RX channels and select the RX Non-DPA option to generate the IP as non-DPA receiver.
  • DPA receiver—specify the Number of RX channels and select the RX DPA-FIFO option to generate the IP as DPA receiver.
  • Soft CDR receiver—specify the Number of RX channels and select the RX Soft-CDR option to generate the IP as soft-CDR receiver.

Each HSIO bank can support up to 47 pairs of transmitter and receiver combinations.

Table 10.  Supported Usage Modes with Number of IP Instances in an I/O BankThis table lists the supported number of LVDS SERDES IP instances based on the usage modes and PLL configurations for one HSIO bank.
Number of Channels Usage Modes PLL Configuration Number of IP Instances

1–47 7

Maximum of 24 transmitter and receiver channels combination per sub-bank.

Transmitters and receivers
  • Internal PLL—you can drive both transmitters and receivers of the same data rate in a single LVDS SERDES instance with an internal PLL
  • External PLL
Same transmitter and receiver data rate 1
Different transmitter and receiver data rates 2
1–47 7 Transmitters External PLL 1
Internal PLL 1
1–47 Receivers External PLL 1
Internal PLL 1
Note: You must use one of the differential pin pairs for the I/O PLL reference clock.
7 One pair of differential pins is used as outclock.