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1. Agilex™ 5 LVDS SERDES Overview
2. Agilex™ 5 LVDS SERDES Architecture
3. Agilex™ 5 LVDS SERDES Transmitter
4. Agilex™ 5 LVDS SERDES Receiver
5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide
6. Agilex™ 5 LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 5 LVDS SERDES Design Guidelines
9. Agilex™ 5 LVDS SERDES Troubleshooting Guidelines
10. LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs Archives
11. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings
5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings
5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings
5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings
5.1.6.6. LVDS SERDES Intel® FPGA IP Clock Resource Summary
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS SERDES Transmitters and Receivers with External PLL
8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
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5.1.3. LVDS SERDES IP Usage Modes
You can implement four usage modes using the LVDS SERDES IP.
- Transmitter—specify the Number of TX channels to generate the IP as a transmitter.
- Non-DPA receiver—specify the Number of RX channels and select the RX Non-DPA option to generate the IP as non-DPA receiver.
- DPA receiver—specify the Number of RX channels and select the RX DPA-FIFO option to generate the IP as DPA receiver.
- Soft CDR receiver—specify the Number of RX channels and select the RX Soft-CDR option to generate the IP as soft-CDR receiver.
Each HSIO bank can support up to 47 pairs of transmitter and receiver combinations.
Number of Channels | Usage Modes | PLL Configuration | Number of IP Instances | |
---|---|---|---|---|
1–47 7 Maximum of 24 transmitter and receiver channels combination per sub-bank. |
Transmitters and receivers |
|
Same transmitter and receiver data rate | 1 |
Different transmitter and receiver data rates | 2 | |||
1–47 7 | Transmitters | External PLL | 1 | |
Internal PLL | 1 | |||
1–47 | Receivers | External PLL | 1 | |
Internal PLL | 1 |
Note: You must use one of the differential pin pairs for the I/O PLL reference clock.
7 One pair of differential pins is used as outclock.