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1. Agilex™ 5 LVDS SERDES Overview
2. Agilex™ 5 LVDS SERDES Architecture
3. Agilex™ 5 LVDS SERDES Transmitter
4. Agilex™ 5 LVDS SERDES Receiver
5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide
6. Agilex™ 5 LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 5 LVDS SERDES Design Guidelines
9. Agilex™ 5 LVDS SERDES Troubleshooting Guidelines
10. LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs Archives
11. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings
5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings
5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings
5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings
5.1.6.6. LVDS SERDES Intel® FPGA IP Clock Resource Summary
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS SERDES Transmitters and Receivers with External PLL
8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
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4.3.2. DPA Mode
The DPA block selects the best possible dpa_fast_clock from the eight fast clock signals generated by the I/O PLL.
The receiver uses these serial clock signals for the following functions:
- dpa_fast_clock— writing serial data into the synchronizer
- fast_clock—reading serial data from the synchronizer, data realignment, and deserializer blocks
In DPA mode, the DPA FIFO synchronizes the retimed data to the LVDS SERDES clock domain. The DPA clock may shift the phase during the initial lock period. To avoid data run-through conditions caused by the FIFO write pointer creeping up to the read pointer, hold the FIFO in reset state until the DPA locks.
Figure 19. Receiver Data Path Block Diagram—DPA ModeIn this figure, all the receiver hardware blocks are active.
Note: In DPA mode, you can place receiver channels of a SERDES instance in both I/O sub-banks. However, you must drive the channels in each sub-bank with different PLLs.