Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 4/01/2024
Public

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Document Table of Contents

1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 4.0.0
The Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices is a configurable intellectual property (IP) core that complies with the IEEE 802.3 standard.

It incorporates a 10/100/1000 Mbps Ethernet media access controller (MAC) and 1000BASE-X/SGMII physical coding sublayer (PCS) with an embedded physical medium attachment (PMA) built with on-chip transceiver I/Os. When offered in MAC-only mode, the IP connects with an external PHY chip using Media Independent Interface (MII), Gigabit Media Independent Interface (GMII), or Reduced Gigabit Media Independent Interface (RGMII).