AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 2/12/2024
Public

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Document Table of Contents

4.6. Configuration Space Extension

The Hard IP implements mandatory PCI* and PCIe* capabilities. The AXI Streaming Intel® FPGA IP for PCI Express* provides the Configuration Extension Bus (CEB) interface to extend the configuration capabilities available in an IP's protocol stack HIP block.

  • The configuration TLPs with a destination address not matching with internally implemented registers are routed to the configuration extension interface.
  • The user application is responsible for returning data on read.
  • The user application returns zero if a transaction targets unimplemented address space.
  • The write access to unimplemented address is dropped by application.
  • Maximum one outstanding read request is allowed.
  • The next pointer field of the last capability structure within HIP is set by the external capability pointer parameter.
    • Separate parameters are provided for PCI* Compatible Region of Physical Function (PF) and Virtual Function (VF).
    • Separate parameters are provided for PCIe* extended capability region of Physical Function (PF) and Virtual Function (VF).
  • The IP implements timeout mechanism for request issued on the CEB interface.
    • The timeout value is configurable, and you can set this value during compilation.
    • The IP sends the completion back to the host with "SC" status and data as all zeros in case the application failed to return data before the timeout counter expires.
Note: The CEB interface and the CII interface are mutually exclusive. Hence, both cannot be enabled at the same time.
Note: Refer to Interfaces and Signals for details on the interface signals.