AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 790711
Date 2/12/2024
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express* 4. IP Architecture and Functional Description 5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters 6. Interfaces and Signals 7. Register Descriptions 8. Document Revision History for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Specifications B. Simulating the Design Example
1. Introduction x
1.1. Goal of the AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.2. Intended Audience for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. What is PCI Express* ? 1.4. What are the Intel® FPGA IPs for PCI Express* ? 1.5. What is the AXI Streaming Intel® FPGA IP for PCI Express* ? 1.6. Example Use Models 1.7. Design Flow Requirements
1.7. Design Flow Requirements x
1.7.1. Design Software 1.7.2. Hardware
2. Features x
2.1. Supported Features 2.2. Device Family Support 2.3. Performance
3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express* x
3.1. Download and Install Quartus Software 3.2. Obtain and Install Intel FPGA IPs and Licenses 3.3. Configure and Generate the AXI Streaming Intel® FPGA IP for PCI Express* 3.4. Instantiate and Connect the AXI Streaming Intel® FPGA IP for PCI Express* Interfaces 3.5. Simulate the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.6. Compile the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.7. Software Drivers for AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.8. Build the Application for the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.9. Verification with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.10. Debugging with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
3.4. Instantiate and Connect the AXI Streaming Intel® FPGA IP for PCI Express* Interfaces x
3.4.1. Clocking and Resets 3.4.2. Application Packet Datapath 3.4.3. Enabling Additional Features 3.4.4. Enabling Optional Interfaces
3.5. Simulate the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.5.1. Simulating the Design Example
3.5.1. Simulating the Design Example x
3.5.1.1. Steps to Run Simulations
3.5.1.1. Steps to Run Simulations x
3.5.1.1.1. VCS* Simulator
3.7. Software Drivers for AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.7.1. Installing the Linux Kernel Driver
3.8. Build the Application for the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.8.1. Running the Design Example
3.8.1. Running the Design Example x
3.8.1.1. Running the PIO Design Example
3.10. Debugging with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.10.1. Debugging Link Training Issues 3.10.2. Debugging Data Transfer and Performance Issues
3.10.1. Debugging Link Training Issues x
3.10.1.1. Operating System Tools and Utilities 3.10.1.2. Signal Tap Logic Analyzer 3.10.1.3. Additional Debug Tools
3.10.2. Debugging Data Transfer and Performance Issues x
3.10.2.1. Advanced Error Reporting (AER) 3.10.2.2. Second-Level Debug Tools
4. IP Architecture and Functional Description x
4.1. Clocks and Resets 4.2. PCIe Hard IP (HIP) 4.3. HIP Interface (IF) Adaptor 4.4. Application Error Reporting 4.5. Debug Toolkit and Hard IP (HIP) Reconfiguration Interface 4.6. Configuration Space Extension 4.7. Control Shadow 4.8. Configuration Intercept Interface 4.9. Power Management 4.10. Legacy Interrupt 4.11. Credit Handling 4.12. Completion Timeout 4.13. Transaction Ordering 4.14. Page Request Service (PRS) Events 4.15. TX Non-Posted Metering Requirement on Application 4.16. MSI Pending 4.17. D-State Status 4.18. Configuration Retry Status Enable 4.19. AXI-Streaming Interface 4.20. Precision Time Measurement (PTM) [F/R-Tiles Only]
5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters x
5.1. Parameter Editor Parameters
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. Application Packet Interface 6.4. Configuration Extension Bus Interface 6.5. Configuration Intercept Interface 6.6. Function Level Reset Interface 6.7. Control Shadow Interface (st_ctrlshadow) 6.8. Completion Timeout Interface (st_cplto) 6.9. Miscellaneous Signals 6.10. Control and Status Register Responder Interface (lite_csr) 6.11. VF Error Flag Interface (vf_err/sent_vfnonfatalmsg) 6.12. VIRTIO PCI* Configuration Access Interface 6.13. Serial Data Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals
6.3. Application Packet Interface x
6.3.1. Header Format 6.3.2. Prefix Format 6.3.3. Function Number Format 6.3.4. BAR Number Format 6.3.5. Data and Header Packing Schemes 6.3.6. Application Packet Transmit Interface (st_tx) 6.3.7. Application Packet Receive Interface (st_rx) 6.3.8. Flow Control Credit Handling
6.3.5. Data and Header Packing Schemes x
6.3.5.1. HIP Native Mode Packing 6.3.5.2. Compact Packing 6.3.5.3. Simple Packing
6.3.5.1. HIP Native Mode Packing x
6.3.5.1.1. Application Logic Guidelines for the AXI Streaming TX Interface in HIP Native Mode (R-Tile) 6.3.5.1.2. Application Logic Guidelines for the AXI Streaming RX Interface in HIP Native Mode
6.3.5.2. Compact Packing x
6.3.5.2.1. Application Logic Guidelines for the AXI Streaming TX Interface in Compact Mode (P/R-Tiles) 6.3.5.2.2. Application Logic Guidelines for the AXI Streaming RX Interface in Compact Mode (P/R-Tiles)
6.3.5.3. Simple Packing x
6.3.5.3.1. Application Logic Guidelines for the AXI Streaming TX Interface in Simple Mode (P/R-Tiles) 6.3.5.3.2. Application Logic Guidelines for the AXI Streaming RX Interface in Simple Mode (P/R-Tiles)
6.3.8. Flow Control Credit Handling x
6.3.8.1. Application Transmit Flow Control Credit Interface (st_txcrdt) 6.3.8.2. Application Receive Flow Control Credit Interface (st_rxcrdt) (R-Tile Only)
6.4. Configuration Extension Bus Interface x
6.4.1. Configuration Extension Bus Request Interface (st_cebreq) 6.4.2. Configuration Extension Bus Response Interface (st_cebresp)
6.5. Configuration Intercept Interface x
6.5.1. Configuration Intercept Request Interface (st_ciireq) 6.5.2. Configuration Intercept Response Interface (st_ciiresp)
6.6. Function Level Reset Interface x
6.6.1. Function Level Reset Received Interface (st_flrrcvd) 6.6.2. Function Level Reset Completion Interface (st_flrcmpl)
6.12. VIRTIO PCI* Configuration Access Interface x
6.12.1. VIRTIO PCI* Config Access Request Interface (st_virtio_pcicfgreq) 6.12.2. VIRTIO PCI* Config Access Completion Interface (st_virtio_pcicfgcmpl)
7. Register Descriptions x
7.1. Register Address Map 7.2. PCIe Configuration Space 7.3. AXI Streaming Intel® FPGA IP for PCI Express* Soft Register Address Map
7.2. PCIe Configuration Space x
7.2.1. PCIe Configuration Space Registers
7.3. AXI Streaming Intel® FPGA IP for PCI Express* Soft Register Address Map x
7.3.1. AXI Streaming Intel® FPGA IP for PCI Express* Control Registers 7.3.2. IP Debug Registers 7.3.3. IP Performance Monitor Registers
7.3.1. AXI Streaming Intel® FPGA IP for PCI Express* Control Registers x
7.3.1.1. AXI Streaming Intel® FPGA IP for PCI Express* Version 7.3.1.2. AXI Streaming Intel® FPGA IP for PCI Express* Features 7.3.1.3. AXI Streaming Intel® FPGA IP for PCI Express* Interface Attributes 7.3.1.4. ERROR GEN CTRL 7.3.1.5. ERROR GEN ATTR 7.3.1.6. ERROR TLP Header DW0-3 7.3.1.7. ERROR TLP Prefix 7.3.1.8. HOT PLUG GEN CTRL 7.3.1.9. POWER MANAGEMENT CTRL 7.3.1.10. LEGACY INTERRUPT CTRL 7.3.1.11. CFG REG IA CTRL 7.3.1.12. CFG REG IA FN NUM 7.3.1.13. CFG REG IA WRDATA 7.3.1.14. CFG REG IA RDDATA 7.3.1.15. PRS CTRL 7.3.1.16. MSI PENDING CTRL 7.3.1.17. MSI PENDING 7.3.1.18. D-STATE STS 7.3.1.19. CFG RETRY CTRL
7.3.2. IP Debug Registers x
7.3.2.1. HIP Status 7.3.2.2. HIP BP CYCLES 7.3.2.3. HIA BP CYCLES 7.3.2.4. APP BP CYCLES 7.3.2.5. HIA RX BP CYCLES
7.3.3. IP Performance Monitor Registers x
7.3.3.1. PERFMON CTRL 7.3.3.2. TX MRD TLP 7.3.3.3. TX MWR TLP 7.3.3.4. TX MSG TLP 7.3.3.5. TX CFGWR TLP 7.3.3.6. TX CFGRD TLP 7.3.3.7. RX MRD TLP 7.3.3.8. RX MWR TLP 7.3.3.9. RX MSG TLP 7.3.3.10. RX CFGWR TLP 7.3.3.11. RX CFGRD TLP 7.3.3.12. TX MEM DATA 7.3.3.13. TX CPL DATA 7.3.3.14. RX MEM DATA 7.3.3.15. RX CPL DATA
A. Specifications x
A.1. P-Tile Specifications A.2. F-Tile Specifications A.3. R-Tile Specifications
A.1. P-Tile Specifications x
A.1.1. P-Tile Completion Buffer Size A.1.2. Power Management A.1.3. MSI and MSI-X
A.2. F-Tile Specifications x
A.2.1. F-Tile Completion Buffer Size A.2.2. Power Management
A.3. R-Tile Specifications x
A.3.1. R-Tile Completion Buffer Size A.3.2. Power Management A.3.3. MSI and MSI-X
B. Simulating the Design Example x
B.1. Testbench
B.1. Testbench x
B.1.1. Testbench Modules B.1.2. Test Driver Module B.1.3. PIO Design Example Testbench B.1.4. Root Port BFM
1. Introduction
2. Features
3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express*
4. IP Architecture and Functional Description
5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters
6. Interfaces and Signals
7. Register Descriptions
8. Document Revision History for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Specifications
B. Simulating the Design Example

3.10.2.1. Advanced Error Reporting (AER)

Each PCI Express* compliant device must implement a basic level of error management and can optionally implement advanced error management. The PCI Express* Advanced Error Reporting Capability is an optional Extended Capability that may be implemented by PCI Express* device functions supporting advanced error control and reporting.

The AXI Streaming Intel® FPGA IP for PCI Express* implements both basic and advanced error reporting. Error handling for a Root Port is more complex than that of an Endpoint. In this IP, the Physical Functions (PFs) are always capable of AER (enabled by default). There is no AER implementation for Virtual Functions (VFs).

Use the AER capability of the IP to identify the type of error and the protocol stack layer in which the error may have occurred. Refer to the PCI Express* Capability Structures section of the Configuration Space Registers appendix for the AER Extended Capability Structure and the associated registers.

Table 15.  Correctable Error Status Register (AER)
Observation Issue Resolution
Receiver error bit set Physical layer error which may be due to a PCS error when a lane is in L0, or a Control symbol being received in the wrong lane, or signal Integrity issues where the link may transition from L0 to the Recovery state. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error. Also refer to the flow chart in Debugging Link Training Issues to obtain more information about the error.
Bad DLLP bit set Data link layer error which may occur when a CRC verification fails. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
Bad TLP bit set Data link layer error which may occur when an LCRC verification fails or when a sequence number error occurs. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
Replay_num_rollover bit set Data link layer error which may be due to TLPs sent without success (no ACK) four times in a row. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
replay timer timeout status bit set Data link layer error which may occur when no ACK or NAK was received within the timeout period for the TLPs transmitted. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
Advisory non-fatal Transaction layer error which may be due to higher priority uncorrectable error detected. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
Corrected internal error bits set Transaction layer error which may be due to an ECC error in the internal Hard IP RAM. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
Table 16.  Uncorrectable Error Status Register (AER)
Observation Issue Resolution
Data link protocol error Data link layer error which may be due to transmitter receiving an ACK/NAK whose Seq ID does not correspond to an unacknowledged TLP or ACK sequence number. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
Surprise down error Data link layer error which may be due to link going down during L0, indicating the physical layer link is going down unexpectedly. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
Flow control protocol error Transaction layer error which can be due to the receiver reporting more than the allowed credit limit. This error occurs when a component does not receive updated flow control credits with the 200 μs limit. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers, TX/RX flow control credit interfaces to obtain more information about the error.
Poisoned TLP received Transaction layer error which can be due to a received TLP with the EP bit set. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
Completion timeout Transaction layer error which can be due to a completion not received within the required amount of time after a non-posted request was sent. Use the Control and Status Register Responder Interface (lite_csr), completion timeout interface to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
Completer abort Transaction layer error which can be due to a completer being unable to fulfill a request due to a problem with the requester or a failure of the completer. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
Unexpected completion Transaction layer error which can be due to a requester receiving a completion that does not match any request awaiting a completion. The TLP is deleted by the Hard IP and not presented to the Application Layer. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
Receiver overflow Transaction layer error which can be due to a receiver receiving more TLPs than the available receive buffer space. The TLP is deleted by the Hard IP and not presented to the Application Layer. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers, TX/RX flow control credit interfaces to obtain more information about the error.
Malformed TLP Transaction layer error which can be due to errors in the received TLP header. The TLP is deleted by the Hard IP and not presented to the Application Layer Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
ECRC error Transaction layer error which can be due to an ECRC check failure at the receiver despite the fact that the TLP is not malformed and the LCRC check is valid. The Hard IP block handles this TLP automatically. If the TLP is a nonposted request, the Hard IP block generates a completion with a completer abort status. The TLP is deleted by the Hard IP and not presented to the Application Layer. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
Unsupported request Transaction layer error which can be due to the completer being unable to fulfill the request. The TLP is deleted in the Hard IP block and not presented to the Application Layer. If the TLP is a non-posted request, the Hard IP block generates a completion with Unsupported Request status. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
ACS violation Transaction layer error which can be due to access control error in the received posted or non-posted request. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error
Uncorrectable internal error Transaction layer error which can be due to an internal error that cannot be corrected by the hardware. Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
Atomic egress blocked Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
TLP prefix blocked EP or RP only Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
Poisoned TLP egress blocked EP or RP only Use the Control and Status Register Responder Interface (lite_csr) to access the PCIe* configuration space registers, IP Debug Registers to obtain more information about the error.
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