AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 2/12/2024
Public

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7.3.1.2. AXI Streaming Intel® FPGA IP for PCI Express* Features

The register indicates features enabled in the AXI Streaming Intel® FPGA IP for PCI Express* during compile time.

Default Value: Set As per Parameter Settings

Table 61.   AXI Streaming Intel® FPGA IP for PCI Express* Feature Registers
Register Name Bit Attribute User Side Description
IP Features 1 1-0 RO

Reflects Functional Mode parameter value

00 - Power User mode

01 - Reserved

10 - Reserved

11 - Reserved

2 RO Reserved
3 RO

Indicates presence of Debug Toolkit block in a design

0 - Debug Toolkit not Present

1 - Debug Toolkit Present

4 RO Reserved
5 RO Reserved
8-6 RO

Multiple AXI Stream Support

000 - Single Stream Present

001 - Two Stream Present

All Others - Reserved

10-9 RO

AXI-ST Header and Data Packing Scheme

00 - Simple Packing

10 - Compact Packing

31-11 RO Reserved