AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 2/12/2024
Public

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6.2.2. Interface Reset Signals

Table 26.  Interface Reset Signals
Signal Name Direction Type Description
pin_perst I Asynchronous This is an active-low input to the PCIe Hard IP. It implements the PERST# function defined by the PCIe specification.
p<n>_pin_perst_n where n = 0, 1, 2, 3 O Asynchronous This is the PERST output signal from the Hard IP. It is derived from the pin_perst_n input signal.
p<n>_Subsystem_cold_rst_n I Could be implemented as synchronous or asynchronous reset. IP global reset. Resets sticky register bits. Active low.
p<n>_Subsystem_warm_rst_n I Could be implemented as synchronous or asynchronous reset. IP warm reset. Does not reset sticky register bits. Active low.
p<n>_Subsystem_cold_rst_ack_n O Asynchronous Handshake signal. Indicates cold reset action is completed by the IP.
p<n>_Subsystem_warm_rst_ack_n O Asynchronous Handshake signal. Indicates warm reset action is completed by the IP.
p<n>_axi_st_areset_n I The reset signal can be asserted asynchronously, but deassertion must be synchronous after the rising edge of axi_st_clk. AXI-Streaming main datapath reset. Active-LOW reset signal. Used to reset the AXI-ST datapath interface.
p<n>_axi_lite_areset_n I The reset signal can be asserted asynchronously, but deassertion must be synchronous after the rising edge of axi_lite_clk. AXI-Lite reset. Active-LOW reset signal. Used to reset the AXI Lite interface.
p<n>_Subsystem_rst_req I Asynchronous

Reset entry indication from Central Reset Sequencer block implemented by the user logic.

p<n>_Subsystem_rst_rdy O Asynchronous Ready signal for reset entry indication from the IP to the Central Reset Sequencer block.
p<n>_initiate_warmrst_req O Asynchronous

Warm Reset entry required indication from the IP block to the Central Reset Sequencer in user logic.

Initiator block cannot issue new reset entry request until previous reset sequence (entire reset operation) is completed.

p<n>_initiate_rst_req_rdy I Asynchronous Indicates the Central Reset Sequencer block in the user logic has accepted the initiation request and will start issuing resets.
p<n>_reset_status_n O Synchronous to coreclkout_hip of Hard IP

Active low signal. When asserted, indicates HARD IP is in reset state. When asserted, will continue to stay asserted until pin perstn is deasserted and HARD IP is out of reset state.

The application logic can use this signal to drive its reset network.

The reset_status_n output of HIP drives this signal.

Note: You must implement the user reset sequencer in your application user logic and follow the assertion and deassertion sequence for graceful entry and exit for each of the resets (cold, warm etc). The following figure shows the reset connections between a user-implemented reset controller and the AXI Streaming Intel® FPGA IP for PCI Express* .
Figure 28. User Reset Controller Connections

The following table indicates the signals/blocks used for each type of reset:

Table 27.  Signals and Blocks Used for Reset Type
Reset Type Signals/Blocks Under Reset
Cold Reset
  • Subsystem_cold_rst_n and Subsystem_warm_rst_n will be asserted
  • Bus resets (AXI-ST/AXI-MM/AXI-Lite) will be asserted
  • HIP will undergo reset

Warm Reset

(e.g., LTSSM Hot reset)

  • Subsystem_cold_rst_n will not be asserted
  • Bus resets (AXI-ST/AXI-MM/AXI-Lite) will be asserted also
  • HIP will undergo reset also

Expected reset isolation requirement for reset domain crossings are shown in the following table.

Table 28.  Reset Isolation Requirement for Reset Domain Crossings
  • No: No reset isolation required for Column->Row Reset Domain Crossing
  • Yes: Reset isolation required for Column->Row Reset Domain Crossing
  • N/A: Not applicable since same Reset Domain Crossing

Column: Source

Row: Destination

Cold Reset HIP Reset Warm Reset AXI-ST/MM Reset AXI-Lite Reset
Cold Reset N/A No Yes No No
HIP Reset No N/A No No No
Warm Reset No No N/A No No
AXI-ST Reset No No No N/A No
AXI-Lite Reset No No No No N/A
Note: In Endpoint mode, IP warm reset could be asserted without IP cold reset in scenarios such LTSSM Hot Reset.

Cold Reset Entry and Exit Sequence

The following is the sequence for Cold Reset Entry.

  1. Cold reset is initiated by the assertion of Hard IP’s p*_pin_perst_n.
  2. Hard IP asserts pld_link_reset_req to the AXI IP soft logic.
  3. The AXI IP notifies the user reset sequencer by asserting initiate_warmrst_req.
  4. User reset sequencer then asserts _rst_req.
  5. The AXI IP sequences its internal blocks for reset entry (intA_rst_req, intB_rst_req, intA_rst_rdy, intB_rst_rdy, …).
  6. The AXI IP asserts Subsystem_rst_rdy to user reset sequencer, indicating the IP's internal blocks are ready for reset.
  7. User reset sequencer acknowledges to the AXI IP that it is ready for reset by asserting initiate_rst_req_rdy.
  8. The AXI IP soft logic then asserts pld_warm_rst_rdy to Hard IP.
  9. Hard IP asserts reset_status_n indicating the application logic needs to be in reset.
  10. User reset sequencer asserts Subsystem_cold_rst_n, Subsystem_warm_rst_n and AXI bus resets.
Figure 29. Cold Reset Entry and Exit Sequence Timing Diagram
Note: * indicates the signals between the AXI Streaming Intel® FPGA IP for PCI Express* soft logic and the Hard IP. These signals are not available to the application logic.

Warm Reset Entry & Exit Sequence

The following is the sequence for Warm Reset Entry.

  1. Warm reset is initiated by the assertion of Hard IP event, e.g., Hot reset.
  2. Hard IP asserts pld_link_reset_req to the AXI IP soft logic.
  3. The AXI IP notifies the user reset sequencer by asserting initiate_warmrst_req.
  4. The user reset sequencer asserts Subsystem_rst_req.
  5. The AXI IP sequences its internal blocks for reset entry (intA_rst_req, intB_rst_req, intA_rst_rdy, intB_rst_rdy, …).
  6. The AXI IP asserts Subsystem_rst_rdy to the user reset sequencer, indicating the IP's internal blocks are ready for reset.
  7. The user reset sequencer acknowledges to the IP that it is ready for reset by asserting initiate_rst_req_rdy.
  8. The AXI IP soft logic then asserts pld_warm_rst_rdy to Hard IP.
  9. Hard IP asserts reset_status_n indicating the application logic needs to be in reset.
  10. The user reset sequencer asserts Subsystem_warm_rst_n and AXI bus resets.
Note: Warm Reset flow is similar to Cold Reset flow, with the exception that p*_pin_perst_n and Subsystem_cold_rst_n are not asserted for warm reset
Figure 30. Warm Reset Entry and Exit Sequence Timing Diagram
Note: * indicates the signals between the AXI Streaming Intel® FPGA IP for PCI Express* soft logic and the Hard IP. These signals are not available to the application logic.

User reset sequencer initiated Cold Reset Entry and Exit Sequence

  1. Cold reset is initiated by the user reset sequencer by the assertion of the Subsystem_rst_req.
  2. The AXI IP sequences its internal blocks for reset entry (intA_rst_req, intB_rst_req, intA_rst_rdy, intB_rst_rdy, …).
  3. The AXI IP asserts Subsystem_rst_rdy to user reset sequencer, indicating the IP's internal blocks are ready for reset.
  4. The user reset sequencer asserts Subsystem_cold_rst_n, Subsystem_warm_rst_n and AXI bus resets.
Figure 31. User Reset Sequencer Initiated Cold Reset Entry and Exit Sequence Timing Diagram
Note: * indicates the signals between the AXI Streaming Intel® FPGA IP for PCI Express* soft logic and the Hard IP. These signals are not available to the application logic.

User reset sequencer triggered Warm Reset flow is the same as the user reset sequencer triggered Cold Reset flow, with the exception that the Subsystem_cold_rst_n will not be asserted for this flow.

Figure 32. User Reset Sequencer Initiated Warm Reset Entry and Exit Sequence Timing Diagram
Note: * indicates the signals between the AXI Streaming Intel® FPGA IP for PCI Express* soft logic and the Hard IP. These signals are not available to the application logic.