AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 2/12/2024
Public

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Document Table of Contents

6.3.1. Header Format

The following table lists header fields, their byte positions and bit positions on the user header bus.

Table 30.  Header Format
Header Byte Index Header Fields Bits Header Bit Position Start Header Bit Position End
Byte 15 - Byte 0 PCIe* Header 128 0 127
Byte 19 - Byte 16 Prefix 24 128 151
Prefix Type 5 152 156
Prefix Present 1 157 157
Reserved 2 158 159
Byte 23 - Byte 20 PF Number 3 160 162
VF Number 11 163 173
VF Active 1 174 174
BAR number 4 175 178
Slot number 5 179 183
Reserved* 8 184 191
Byte 31 - Byte 24 Reserved 64 192 255
Note: Bits [186:185] are reserved for future use.

The following figure shows a standard PCIe header format.

Figure 33.  PCIe* Header for Memory TLP with 64Bit Addressing (4DW Header)

The PCI* specification standard header format is mapped to a Tuser Header interface as shown in the following figure:

Figure 34. 4DW PCIe* Header Mapping on the User Header Bus

The 3DW PCIe* Header will be mapped to AXI-ST Tdata bit[95:0], the bit[127:96] are considered do not care in this case.

Figure 35.  PCIe* Header for Memory TLP with 64Bit Addressing (3DW Header)
Figure 36. 3DW PCIe* Mapping on the User Header Bus