AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 2/12/2024
Public

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6.12.2. VIRTIO PCI* Config Access Completion Interface (st_virtio_pcicfgcmpl)

Table 56.   VIRTIO PCI* Configuration Access Completion Interface
Signal Name Direction Clock Domain Description
app_ss_virtio_pcicfgcmpl_tvalid Input axi_lite_clk When asserted, indicates a VIRTIO PCI* Configuration Access Completion to be returned to HOST. The signal is valid for one clock cycle.
app_ss_virtio_pcicfgcmpl_tdata[31:0] Input axi_lite_clk [31:0] - The completion Data value.