AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 790711
Date 2/12/2024
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express* 4. IP Architecture and Functional Description 5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters 6. Interfaces and Signals 7. Register Descriptions 8. Document Revision History for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Specifications B. Simulating the Design Example
1. Introduction x
1.1. Goal of the AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.2. Intended Audience for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. What is PCI Express* ? 1.4. What are the Intel® FPGA IPs for PCI Express* ? 1.5. What is the AXI Streaming Intel® FPGA IP for PCI Express* ? 1.6. Example Use Models 1.7. Design Flow Requirements
1.7. Design Flow Requirements x
1.7.1. Design Software 1.7.2. Hardware
2. Features x
2.1. Supported Features 2.2. Device Family Support 2.3. Performance
3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express* x
3.1. Download and Install Quartus Software 3.2. Obtain and Install Intel FPGA IPs and Licenses 3.3. Configure and Generate the AXI Streaming Intel® FPGA IP for PCI Express* 3.4. Instantiate and Connect the AXI Streaming Intel® FPGA IP for PCI Express* Interfaces 3.5. Simulate the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.6. Compile the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.7. Software Drivers for AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.8. Build the Application for the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.9. Verification with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.10. Debugging with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
3.4. Instantiate and Connect the AXI Streaming Intel® FPGA IP for PCI Express* Interfaces x
3.4.1. Clocking and Resets 3.4.2. Application Packet Datapath 3.4.3. Enabling Additional Features 3.4.4. Enabling Optional Interfaces
3.5. Simulate the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.5.1. Simulating the Design Example
3.5.1. Simulating the Design Example x
3.5.1.1. Steps to Run Simulations
3.5.1.1. Steps to Run Simulations x
3.5.1.1.1. VCS* Simulator
3.7. Software Drivers for AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.7.1. Installing the Linux Kernel Driver
3.8. Build the Application for the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.8.1. Running the Design Example
3.8.1. Running the Design Example x
3.8.1.1. Running the PIO Design Example
3.10. Debugging with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.10.1. Debugging Link Training Issues 3.10.2. Debugging Data Transfer and Performance Issues
3.10.1. Debugging Link Training Issues x
3.10.1.1. Operating System Tools and Utilities 3.10.1.2. Signal Tap Logic Analyzer 3.10.1.3. Additional Debug Tools
3.10.2. Debugging Data Transfer and Performance Issues x
3.10.2.1. Advanced Error Reporting (AER) 3.10.2.2. Second-Level Debug Tools
4. IP Architecture and Functional Description x
4.1. Clocks and Resets 4.2. PCIe Hard IP (HIP) 4.3. HIP Interface (IF) Adaptor 4.4. Application Error Reporting 4.5. Debug Toolkit and Hard IP (HIP) Reconfiguration Interface 4.6. Configuration Space Extension 4.7. Control Shadow 4.8. Configuration Intercept Interface 4.9. Power Management 4.10. Legacy Interrupt 4.11. Credit Handling 4.12. Completion Timeout 4.13. Transaction Ordering 4.14. Page Request Service (PRS) Events 4.15. TX Non-Posted Metering Requirement on Application 4.16. MSI Pending 4.17. D-State Status 4.18. Configuration Retry Status Enable 4.19. AXI-Streaming Interface 4.20. Precision Time Measurement (PTM) [F/R-Tiles Only]
5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters x
5.1. Parameter Editor Parameters
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. Application Packet Interface 6.4. Configuration Extension Bus Interface 6.5. Configuration Intercept Interface 6.6. Function Level Reset Interface 6.7. Control Shadow Interface (st_ctrlshadow) 6.8. Completion Timeout Interface (st_cplto) 6.9. Miscellaneous Signals 6.10. Control and Status Register Responder Interface (lite_csr) 6.11. VF Error Flag Interface (vf_err/sent_vfnonfatalmsg) 6.12. VIRTIO PCI* Configuration Access Interface 6.13. Serial Data Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals
6.3. Application Packet Interface x
6.3.1. Header Format 6.3.2. Prefix Format 6.3.3. Function Number Format 6.3.4. BAR Number Format 6.3.5. Data and Header Packing Schemes 6.3.6. Application Packet Transmit Interface (st_tx) 6.3.7. Application Packet Receive Interface (st_rx) 6.3.8. Flow Control Credit Handling
6.3.5. Data and Header Packing Schemes x
6.3.5.1. HIP Native Mode Packing 6.3.5.2. Compact Packing 6.3.5.3. Simple Packing
6.3.5.1. HIP Native Mode Packing x
6.3.5.1.1. Application Logic Guidelines for the AXI Streaming TX Interface in HIP Native Mode (R-Tile) 6.3.5.1.2. Application Logic Guidelines for the AXI Streaming RX Interface in HIP Native Mode
6.3.5.2. Compact Packing x
6.3.5.2.1. Application Logic Guidelines for the AXI Streaming TX Interface in Compact Mode (P/R-Tiles) 6.3.5.2.2. Application Logic Guidelines for the AXI Streaming RX Interface in Compact Mode (P/R-Tiles)
6.3.5.3. Simple Packing x
6.3.5.3.1. Application Logic Guidelines for the AXI Streaming TX Interface in Simple Mode (P/R-Tiles) 6.3.5.3.2. Application Logic Guidelines for the AXI Streaming RX Interface in Simple Mode (P/R-Tiles)
6.3.8. Flow Control Credit Handling x
6.3.8.1. Application Transmit Flow Control Credit Interface (st_txcrdt) 6.3.8.2. Application Receive Flow Control Credit Interface (st_rxcrdt) (R-Tile Only)
6.4. Configuration Extension Bus Interface x
6.4.1. Configuration Extension Bus Request Interface (st_cebreq) 6.4.2. Configuration Extension Bus Response Interface (st_cebresp)
6.5. Configuration Intercept Interface x
6.5.1. Configuration Intercept Request Interface (st_ciireq) 6.5.2. Configuration Intercept Response Interface (st_ciiresp)
6.6. Function Level Reset Interface x
6.6.1. Function Level Reset Received Interface (st_flrrcvd) 6.6.2. Function Level Reset Completion Interface (st_flrcmpl)
6.12. VIRTIO PCI* Configuration Access Interface x
6.12.1. VIRTIO PCI* Config Access Request Interface (st_virtio_pcicfgreq) 6.12.2. VIRTIO PCI* Config Access Completion Interface (st_virtio_pcicfgcmpl)
7. Register Descriptions x
7.1. Register Address Map 7.2. PCIe Configuration Space 7.3. AXI Streaming Intel® FPGA IP for PCI Express* Soft Register Address Map
7.2. PCIe Configuration Space x
7.2.1. PCIe Configuration Space Registers
7.3. AXI Streaming Intel® FPGA IP for PCI Express* Soft Register Address Map x
7.3.1. AXI Streaming Intel® FPGA IP for PCI Express* Control Registers 7.3.2. IP Debug Registers 7.3.3. IP Performance Monitor Registers
7.3.1. AXI Streaming Intel® FPGA IP for PCI Express* Control Registers x
7.3.1.1. AXI Streaming Intel® FPGA IP for PCI Express* Version 7.3.1.2. AXI Streaming Intel® FPGA IP for PCI Express* Features 7.3.1.3. AXI Streaming Intel® FPGA IP for PCI Express* Interface Attributes 7.3.1.4. ERROR GEN CTRL 7.3.1.5. ERROR GEN ATTR 7.3.1.6. ERROR TLP Header DW0-3 7.3.1.7. ERROR TLP Prefix 7.3.1.8. HOT PLUG GEN CTRL 7.3.1.9. POWER MANAGEMENT CTRL 7.3.1.10. LEGACY INTERRUPT CTRL 7.3.1.11. CFG REG IA CTRL 7.3.1.12. CFG REG IA FN NUM 7.3.1.13. CFG REG IA WRDATA 7.3.1.14. CFG REG IA RDDATA 7.3.1.15. PRS CTRL 7.3.1.16. MSI PENDING CTRL 7.3.1.17. MSI PENDING 7.3.1.18. D-STATE STS 7.3.1.19. CFG RETRY CTRL
7.3.2. IP Debug Registers x
7.3.2.1. HIP Status 7.3.2.2. HIP BP CYCLES 7.3.2.3. HIA BP CYCLES 7.3.2.4. APP BP CYCLES 7.3.2.5. HIA RX BP CYCLES
7.3.3. IP Performance Monitor Registers x
7.3.3.1. PERFMON CTRL 7.3.3.2. TX MRD TLP 7.3.3.3. TX MWR TLP 7.3.3.4. TX MSG TLP 7.3.3.5. TX CFGWR TLP 7.3.3.6. TX CFGRD TLP 7.3.3.7. RX MRD TLP 7.3.3.8. RX MWR TLP 7.3.3.9. RX MSG TLP 7.3.3.10. RX CFGWR TLP 7.3.3.11. RX CFGRD TLP 7.3.3.12. TX MEM DATA 7.3.3.13. TX CPL DATA 7.3.3.14. RX MEM DATA 7.3.3.15. RX CPL DATA
A. Specifications x
A.1. P-Tile Specifications A.2. F-Tile Specifications A.3. R-Tile Specifications
A.1. P-Tile Specifications x
A.1.1. P-Tile Completion Buffer Size A.1.2. Power Management A.1.3. MSI and MSI-X
A.2. F-Tile Specifications x
A.2.1. F-Tile Completion Buffer Size A.2.2. Power Management
A.3. R-Tile Specifications x
A.3.1. R-Tile Completion Buffer Size A.3.2. Power Management A.3.3. MSI and MSI-X
B. Simulating the Design Example x
B.1. Testbench
B.1. Testbench x
B.1.1. Testbench Modules B.1.2. Test Driver Module B.1.3. PIO Design Example Testbench B.1.4. Root Port BFM
1. Introduction
2. Features
3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express*
4. IP Architecture and Functional Description
5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters
6. Interfaces and Signals
7. Register Descriptions
8. Document Revision History for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Specifications
B. Simulating the Design Example

6.3.8.2. Application Receive Flow Control Credit Interface (st_rxcrdt) (R-Tile Only)

The RX flow control credit interface is not available for P/F-Tiles. The Receive side of the IP operates on an AXI Streaming ready-valid handshake for P- and F-Tiles.

For R-Tile:
  • In HIP Native mode, the IP provides the RX flow control credit interface for the application logic to advertise the available credits in the application to the IP.
  • In non-HIP Native (Simple/Compact) mode, the receive side of the IP operates on an AXI streaming ready-valid handshake. There is no RX flow control credit interface available for the application logic in this mode.

In the R-Tile HIP Native mode, the RX flow control interface provides information on the application's available RX buffer space to the IP for header and data for Posted (P), Non-Posted (NP) and Completion (CPL) transactions. It reports the space available in a number of credits as defined by the PCIe Specification.

The Application logic must ensure that enough credits are provided to the IP initially. This is to prevent a performance impact caused by the lack of credits available between the IP and the Application logic. Depending on the number of P, NP and CPL transactions happening at the PCIe link level, a lack of credit scenario may happen if the number of credits advertised by the Application logic is less than the credits advertised by the IP to the link partner.

Flow control credits are available for the following TLP categories:
  • Posted (P) transactions: TLPs that do not require a response.
  • Non-posted (NP) transactions: TLPs that require a completion.
  • Completions (CPL): TLPs that respond to non-posted transactions.
Table 41.  Credits Advertised by the IP to the Link Partner in Endpoint ModeThe credit unit in this table follows the PCIe Specification where one credit = 4 DWs = 16 Bytes.
Port Posted Headers Posted Data Non-Posted Headers Non-Posted Data Completion Headers Completion Data
Port 0 784 1456 784 392 0 (infinite) 0 (infinite)
Port 1 392 760 392 196 0 (infinite) 0 (infinite)
Note: In some systems, there are broadcast Message TLPs being sent by the link partner during the PCIe enumeration process. Failing to properly initialize and return the corresponding credits from the application logic to the IP may cause enumeration issues due to the priority order between Message TLPs and the Completions required for Configuration TLPs. Application logic must ensure proper credits are returned to the IP for any TLP that it receives.
Table 42.  Categorization of Transaction Types
TLP Type Category
Memory Write Posted
Memory Read Non-Posted
Memory Read Lock
I/O Read
I/O Write
Configuration Read
Configuration Write
Fetch and Add AtomicOp
Message Posted
Completion Completion
Completion with Data
Completion Lock
Completion Lock with Data
Table 43.  Application Receive Flow Control Credit Interface
Signal Name Direction Clock Domain Description
ss_app_st_rxcrdt_tvalid Input axi_st_clk tvalid indicates that the credit information on tdata is valid.
ss_app_st_rxcrdt_tdata[18:0] Input axi_st_clk Carries the credit limit information and type of credit.

[15:0] - Credit Limit Value

[18:16] - Credit Type
  • 3'b000 - Posted Header Credit
  • 3'b001 - Non-Posted Header Credit
  • 3'b010 - Completion Header Credit
  • 3'b011 - Reserved
  • 3'b100 - Posted Data Credit
  • 3'b101 - Non-Posted Data Credit
  • 3'b110 - Completion Data Credit
  • 3'b111 - Reserved

The credit limit is first initialized to 0 for all the credit types.

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