AN 1003: Multi Memory IP System Resource Planning: for Intel Agilex® 7 M-Series FPGAs

Download PDF
ID 788295
Date 11/22/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Component Bandwidth Projections and Limitations 4. Resource Planning for Intel Agilex® 7 M-Series FPGAs 5. Factors Affecting NoC Performance 6. Debugging the NoC 7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs
2. About This Application Note x
2.1. Preliminary Guidelines 2.2. Document Prerequisites 2.3. Terminology for Intel Agilex® 7 M-Series FPGAs
3. Component Bandwidth Projections and Limitations x
3.1. Memory Controller Efficiency 3.2. Hard Memory NoC Bandwidth 3.3. Overall Bandwidth for NoC Systems
3.1. Memory Controller Efficiency x
3.1.1. HBM2E UIB Controller Efficiency 3.1.2. External Memory Interface Controller Efficiency
3.2. Hard Memory NoC Bandwidth x
3.2.1. Horizontal NoC Bandwidth 3.2.2. Initiator NoC Bandwidth 3.2.3. Target NoC Bandwidth 3.2.4. Initiator Target Link Bandwidth
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs x
4.1. Hard Memory NoC Resource Planning Overview 4.2. I/O Bank Blockage 4.3. Planning Avalon® Streaming Utilization 4.4. Planning for Initiator Blockage Impact from GPIO, LVDS SERDES, and PHY Lite Bypass Mode 4.5. Planning NoC PLL and I/O PLL 4.6. Pin Planning for HPS EMIF 4.7. Planning for an External Memory Interface 4.8. Planning for HBM2E 4.9. Planning for the Fabric NoC 4.10. Planning for AXI4-Lite 4.11. Planning NoC and Memory Solution Clocks
4.2. I/O Bank Blockage x
4.2.1. Top Hard Memory NoC 4.2.2. Bottom Hard Memory NoC
4.10. Planning for AXI4-Lite x
4.10.1. Single AXI4 Lite Initiator for Each Horizontal NoC 4.10.2. AXI4-Lite Initiator for HBM2E 4.10.3. AXI4-Lite Initiator for EMIF
4.11. Planning NoC and Memory Solution Clocks x
4.11.1. Clocking without the Fabric NoC 4.11.2. Clocking with the Fabric NoC
5. Factors Affecting NoC Performance x
5.1. Recommended Performance Tuning Procedure 5.2. NoC Initiator and Target Clock Rate 5.3. Recommended NoC Design Topologies 5.4. Traffic Access Pattern and Memory Controller Efficiency 5.5. Traffic Access Pattern Due To Multiple Traffic Flows 5.6. Transaction Size 5.7. Congestion Interaction 5.8. Bandwidth Sharing At Each Switch 5.9. Exceeding NoC Bandwidth Limits 5.10. Maximum Number of Outstanding Transactions 5.11. QoS Priority 5.12. AxID 5.13. Example: 2x2 HBM Crossbars 5.14. Example: 16x16 Crossbar
5.3. Recommended NoC Design Topologies x
5.3.1. 1:1 Connectivity with EMIF and HBM 5.3.2. HBM Crossbars 5.3.3. Connectivity with HPS
6. Debugging the NoC x
6.1. Debugging NoC AXI Transaction Issues 6.2. Debugging NoC Bit Errors 6.3. Debugging NoC Performance Issues
6.3. Debugging NoC Performance Issues x
6.3.1. Measuring Performance with the Signal Tap Logic Analyzer 6.3.2. Measuring Performance with the Performance Monitor 6.3.3. Performance Debug Steps
1. Answers to Top FAQs
2. About This Application Note
3. Component Bandwidth Projections and Limitations
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs
5. Factors Affecting NoC Performance
6. Debugging the NoC
7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs

2.3. Terminology for Intel Agilex® 7 M-Series FPGAs

Table 1.   Intel Agilex® 7 M-Series FPGA Terminology
Term Description
NoC

Network-on-Chip based communications structure between elements only in Intel Agilex® 7 M-Series FPGAs.

Hard Memory NoC The NoC subsystem implemented as a hard block in the Intel® Stratix® 10 M-Series FPGA for interfacing with high-bandwidth memory and external memory interfaces.
Horizontal NoC (HNoC)

The Intel Agilex® 7 M-Series FPGA implements the NoC as two independent hard memory NoCs running horizontally along the top edge and bottom edge of the die.

NoC Initiator (INIU)

The bridge between the AXI4 manager in user logic and the hard memory NoC.

NoC Target (TNIU)

The bridge between the AXI4 subordinate IP in the periphery and the hard memory NoC.

Fabric NoC

An optional implementation of the NoC initiator where the read response data is written directly to M20K memory blocks.

HBM2E

The in-package, high-bandwidth memory available in Intel Agilex® 7 M-Series FPGAs.

Pseudo BL8 Transaction For HBM2E, you can enable data access granularity of 64B (64 bits per Pseudo-Channel at BL8) which can achieve greater efficiency. By default, data access granularity is 32B (64 bits per Pseudo-Channel at BL4).
AXI4 Manager

Function that initiates transactions on an AXI4 interconnect.

AXI4 Subordinate

Function that responds to transactions on an AXI4 interconnect.

GPIO-B Blocks

General purpose I/O bank available in Intel Agilex® 7 M-Series FPGAs.

Bypass Mode Bypasses the NoC. This mode applies only to EMIF configuration, with EMIF in bypass mode.
EMIF in bypass mode Any instance of the External Memory Interfaces (EMIF) IP that you configure with PHY_NOC_EN=false. When PHY_NOC_EN=false, the access mode is through the fabric, in either sync or async mode).
NoC PLL Dedicated phase lock loop (PLL) for the hard memory NoC.
Byte lane (BL) Synonymous with an IO12, or I/O lane.
NoC SSM Subsystem manager for the hard memory NoC.
Secure Device Manager (SDM) There is no connection between the SDM and the hard memory NoC, and all signals from the SDM bypass the hard memory NoC.
UIB Universal interface block that is a silicon bridge to connect FPGA I/O to the HBM2E memory device.
1d1r one dimm, one rank
1d2r one dimm, two ranks
Level Two Title