AN 1003: Multi Memory IP System Resource Planning: for Intel Agilex® 7 M-Series FPGAs

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ID 788295
Date 11/22/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Component Bandwidth Projections and Limitations 4. Resource Planning for Intel Agilex® 7 M-Series FPGAs 5. Factors Affecting NoC Performance 6. Debugging the NoC 7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs
2. About This Application Note x
2.1. Preliminary Guidelines 2.2. Document Prerequisites 2.3. Terminology for Intel Agilex® 7 M-Series FPGAs
3. Component Bandwidth Projections and Limitations x
3.1. Memory Controller Efficiency 3.2. Hard Memory NoC Bandwidth 3.3. Overall Bandwidth for NoC Systems
3.1. Memory Controller Efficiency x
3.1.1. HBM2E UIB Controller Efficiency 3.1.2. External Memory Interface Controller Efficiency
3.2. Hard Memory NoC Bandwidth x
3.2.1. Horizontal NoC Bandwidth 3.2.2. Initiator NoC Bandwidth 3.2.3. Target NoC Bandwidth 3.2.4. Initiator Target Link Bandwidth
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs x
4.1. Hard Memory NoC Resource Planning Overview 4.2. I/O Bank Blockage 4.3. Planning Avalon® Streaming Utilization 4.4. Planning for Initiator Blockage Impact from GPIO, LVDS SERDES, and PHY Lite Bypass Mode 4.5. Planning NoC PLL and I/O PLL 4.6. Pin Planning for HPS EMIF 4.7. Planning for an External Memory Interface 4.8. Planning for HBM2E 4.9. Planning for the Fabric NoC 4.10. Planning for AXI4-Lite 4.11. Planning NoC and Memory Solution Clocks
4.2. I/O Bank Blockage x
4.2.1. Top Hard Memory NoC 4.2.2. Bottom Hard Memory NoC
4.10. Planning for AXI4-Lite x
4.10.1. Single AXI4 Lite Initiator for Each Horizontal NoC 4.10.2. AXI4-Lite Initiator for HBM2E 4.10.3. AXI4-Lite Initiator for EMIF
4.11. Planning NoC and Memory Solution Clocks x
4.11.1. Clocking without the Fabric NoC 4.11.2. Clocking with the Fabric NoC
5. Factors Affecting NoC Performance x
5.1. Recommended Performance Tuning Procedure 5.2. NoC Initiator and Target Clock Rate 5.3. Recommended NoC Design Topologies 5.4. Traffic Access Pattern and Memory Controller Efficiency 5.5. Traffic Access Pattern Due To Multiple Traffic Flows 5.6. Transaction Size 5.7. Congestion Interaction 5.8. Bandwidth Sharing At Each Switch 5.9. Exceeding NoC Bandwidth Limits 5.10. Maximum Number of Outstanding Transactions 5.11. QoS Priority 5.12. AxID 5.13. Example: 2x2 HBM Crossbars 5.14. Example: 16x16 Crossbar
5.3. Recommended NoC Design Topologies x
5.3.1. 1:1 Connectivity with EMIF and HBM 5.3.2. HBM Crossbars 5.3.3. Connectivity with HPS
6. Debugging the NoC x
6.1. Debugging NoC AXI Transaction Issues 6.2. Debugging NoC Bit Errors 6.3. Debugging NoC Performance Issues
6.3. Debugging NoC Performance Issues x
6.3.1. Measuring Performance with the Signal Tap Logic Analyzer 6.3.2. Measuring Performance with the Performance Monitor 6.3.3. Performance Debug Steps
1. Answers to Top FAQs
2. About This Application Note
3. Component Bandwidth Projections and Limitations
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs
5. Factors Affecting NoC Performance
6. Debugging the NoC
7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs

3.2.3. Target NoC Bandwidth

NoC targets are the bridges between AXI4 subordinate EMIF or HBM2E IP in the periphery, and the hard memory NoC. The number of NoC targets in your design and their associated bandwidth depends on the type of memory resource that your design uses. A NoC target is always connected to a specific memory controller, and the NoC target's location relative to the memory controller is always fixed.

The EMIF target operating frequency changes with memory protocol, memory frequency, and device speed grade, as External Memory Interface Target Frequency shows.

Table 6.  External Memory Interface Target Frequency
Device Speed Grade DDR4 Single TNIU Maximum Frequency (MHz) DDR5 Single TNIU Maximum Frequency (MHz) LPDDR5 Single TNIU Maximum Frequency (MHz)
-1 800 700 687.5
-2 800 700 687.5
-3 666.5 600 600

For DDR4 memory, the TNIU bandwidth exceeds the memory bandwidth for all speed grades. This means that if you use the full TNIU bandwidth, backpressure occurs on the NoC. The maximum data rate for DDR4 is 3200 Mbps. This maximum data rate means that the maximum bandwidth that DDR4 can accommodate is 3200Mbps x 32b= = 12.8 GBps. In contrast, the TNIU bandwidth is 25.6 GBps, which is double the bandwidth of the DDR4 memory.

HBM2E Target Frequency shows the fixed operating frequency of the HBM2E target for a given memory protocol and device speed grade.

Table 7.  HBM2E Target Frequency
Device Speed Grade HBM2E Single TNIU Frequency (MHz)
-1 800
-2 700
-3 500

The following equation applies:

Where:

  • Target Data Width = 256 bit or 32B
  • TNIU Frequency = refer to listed frequency per device speed grade in HBM2E Target Frequency

On a -2 speed grade device, you can expect to achieve a maximum bandwidth of 22.4 GBps per single EMIF DDR5 target and single HBM2E pseudo channel target running at 700Mhz.

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