AN 1003: Multi Memory IP System Resource Planning: for Intel Agilex® 7 M-Series FPGAs

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ID 788295
Date 11/22/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Component Bandwidth Projections and Limitations 4. Resource Planning for Intel Agilex® 7 M-Series FPGAs 5. Factors Affecting NoC Performance 6. Debugging the NoC 7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs
2. About This Application Note x
2.1. Preliminary Guidelines 2.2. Document Prerequisites 2.3. Terminology for Intel Agilex® 7 M-Series FPGAs
3. Component Bandwidth Projections and Limitations x
3.1. Memory Controller Efficiency 3.2. Hard Memory NoC Bandwidth 3.3. Overall Bandwidth for NoC Systems
3.1. Memory Controller Efficiency x
3.1.1. HBM2E UIB Controller Efficiency 3.1.2. External Memory Interface Controller Efficiency
3.2. Hard Memory NoC Bandwidth x
3.2.1. Horizontal NoC Bandwidth 3.2.2. Initiator NoC Bandwidth 3.2.3. Target NoC Bandwidth 3.2.4. Initiator Target Link Bandwidth
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs x
4.1. Hard Memory NoC Resource Planning Overview 4.2. I/O Bank Blockage 4.3. Planning Avalon® Streaming Utilization 4.4. Planning for Initiator Blockage Impact from GPIO, LVDS SERDES, and PHY Lite Bypass Mode 4.5. Planning NoC PLL and I/O PLL 4.6. Pin Planning for HPS EMIF 4.7. Planning for an External Memory Interface 4.8. Planning for HBM2E 4.9. Planning for the Fabric NoC 4.10. Planning for AXI4-Lite 4.11. Planning NoC and Memory Solution Clocks
4.2. I/O Bank Blockage x
4.2.1. Top Hard Memory NoC 4.2.2. Bottom Hard Memory NoC
4.10. Planning for AXI4-Lite x
4.10.1. Single AXI4 Lite Initiator for Each Horizontal NoC 4.10.2. AXI4-Lite Initiator for HBM2E 4.10.3. AXI4-Lite Initiator for EMIF
4.11. Planning NoC and Memory Solution Clocks x
4.11.1. Clocking without the Fabric NoC 4.11.2. Clocking with the Fabric NoC
5. Factors Affecting NoC Performance x
5.1. Recommended Performance Tuning Procedure 5.2. NoC Initiator and Target Clock Rate 5.3. Recommended NoC Design Topologies 5.4. Traffic Access Pattern and Memory Controller Efficiency 5.5. Traffic Access Pattern Due To Multiple Traffic Flows 5.6. Transaction Size 5.7. Congestion Interaction 5.8. Bandwidth Sharing At Each Switch 5.9. Exceeding NoC Bandwidth Limits 5.10. Maximum Number of Outstanding Transactions 5.11. QoS Priority 5.12. AxID 5.13. Example: 2x2 HBM Crossbars 5.14. Example: 16x16 Crossbar
5.3. Recommended NoC Design Topologies x
5.3.1. 1:1 Connectivity with EMIF and HBM 5.3.2. HBM Crossbars 5.3.3. Connectivity with HPS
6. Debugging the NoC x
6.1. Debugging NoC AXI Transaction Issues 6.2. Debugging NoC Bit Errors 6.3. Debugging NoC Performance Issues
6.3. Debugging NoC Performance Issues x
6.3.1. Measuring Performance with the Signal Tap Logic Analyzer 6.3.2. Measuring Performance with the Performance Monitor 6.3.3. Performance Debug Steps
1. Answers to Top FAQs
2. About This Application Note
3. Component Bandwidth Projections and Limitations
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs
5. Factors Affecting NoC Performance
6. Debugging the NoC
7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs

3.1.1. HBM2E UIB Controller Efficiency

For each HBM2E DRAM in an Intel Agilex® 7 M-Series FPGA, there are eight channels of 128-bits each, or 16 pseudo channels of 64-bits each.

The following equation calculates the ideal bandwidth that a memory can achieve, based on 100% controller efficiency:



For example, for a -1 speed grade device with a HBM2E interface running at 1.6 GHz, the ideal bandwidth per pseudo channel is: 

(64 DQ × 1.6 GHz x 2)/8 = 25.6 GBps

Likewise, at -2 and -3 device speed grade, a single pseudo channel provides 22.4 GBps and 16 GBps, respectively.

HBM2E Controller Efficiency Preliminary Data shows the HBM2E controller efficiency specifications for various speed grades when using pseudo BL8 transfers. HBM2E Controller Efficiency Preliminary Data shows that sequential memory access demonstrates a higher typical efficiency compared to random memory access.

Table 2.  HBM2E Controller Efficiency Preliminary Data for -3 Device Speed Grade (2.0 GT/s), -2 Device Speed Grade (2.8 GT/s) and -1 Device Speed Grade (3.2 GT/s)
Access Pattern Read (%) Write (%) Controller Efficiency Specification (%)
2.0 GT/s 2.8 GT/s 3.2 GT/s
Sequential 50 50 > 80 > 70 > 65
Sequential 100 0 > 90 > 90 > 90
Sequential 0 100 > 90 > 90 > 90
Random 50 50 > 65 > 55 > 50
Random 100 0 > 65 > 55 > 50
Random 0 100 > 65 > 55 > 50
Note: HBM2E Controller Efficiency Preliminary Data reflects the specifications that the controller is designed to meet, and not actual measured efficiency data.

The per pseudo channel bandwidth of HBM2E for an FPGA depends on the following factors:

  • Data rate per bit
  • Data bus width
  • Data bus efficiency (percentage of time data is actively being transferred)

The following equation expresses the total effective bandwidth per interface as a function of all these factors:



If the HBM2E controller operates at 90% efficiency, the effective bandwidth is 23.04 GBps (25.6 GBps x 0.9) per pseudo channel, running at 1.6 GHz -1 speed grade. A single HBM2E, with 16 pseudo channels running at 1.6GHz, provides a total of 409.6GBps bandwidth.

You must account for HBM2E controller efficiency across various traffic scenarios that a memory can achieve (or that a memory can service) while determining overall system performance through the hard memory NoC.

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