Intel® Simics® Simulator for Intel® FPGAs: Intel Agilex® 5 E-Series Virtual Platform User Guide

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ID 786901
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About This Document 2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms 3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model 5. Supported Use Cases A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms x
2.1. Intel Agilex® 5 E-Series Universal Virtual Platform
2.1. Intel Agilex® 5 E-Series Universal Virtual Platform x
2.1.1. Intel Agilex® 5 E-Series Universal Virtual Platform Overview 2.1.2. Intel Agilex® 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.1.3. Intel Agilex® 5 E-Series Virtual Platform Key Capabilities
2.1.1. Intel Agilex® 5 E-Series Universal Virtual Platform Overview x
2.1.1.1. Intel Agilex® 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Intel Agilex® 5 E-Series Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges
3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components
3.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model x
3.1.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Intel Agilex® 5 E-Series HPS Components
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Intel Agilex® 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms
3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model
5. Supported Use Cases
A. Document Revision History

2.1.2. Intel Agilex® 5 E-Series Universal Virtual Platform User-Configurable Parameters

The Intel Agilex® 5 E-Series Universal Virtual Platform has the following user-configurable parameters provided in the target script:

Table 5.   Intel Agilex® 5 E-Series Universal Virtual Platform Parameters
Parameter Description
create_hps_eth0_network

Create a basic Ethernet network and connect it to the eth0 peripheral of the Hard Processor System Intel Agilex® 5 FPGA IP.

  • Range: Boolean
  • Default value: True
create_hps_sd_card

Create the SD card in the board component and connect it to the SD/eMMC controller. You can set either the create_hps_sd_card or create_hps_mmc parameter to true at a time.

  • Range: Boolean
  • Default value: True
create_hps_mmc

Create the eMMC card in the board component and connect it to the SD/eMMC controller. You can set either the create_hps_sd_card or create_hps_mmc parameter to true at a time.

  • Range: Boolean
  • Default value: False
create_hps_serial0_console

Create a console component and connect it to the serial0 peripheral of the Hard Processor System Intel Agilex® 5 FPGA IP.

  • Range: Boolean
  • Default value: True
fsbl_image_filename

First stage bootloader file. Supported format is .bin .

  • Range: File name string.
  • Default value: ""
hps_boot_core

The CPU to use as the boot core.

  • Range: Integer: [0,2]
  • Default value: 0
hps_core0_1_power_on

The power-on states of CPU 0/1.

  • Range: Boolean
  • Default value: True
hps_core2_power_on

The power-on state of CPU 2.

  • Range: Boolean
  • Default value: True
hps_core3_power_on

The power-on state of CPU 3.

  • Range: Boolean
  • Default value: True
sd_image_filename

Name of the SD image to load into the SD memory model of the board component. The supported format is .craff, .img, or .wic.

  • Range: File name string.
  • Default value: ""
nand_data_image_filename

Name of the NAND image to load into the NAND memory model of the board component. The supported format is raw binary (.bin or .craff).

  • Range: File name string.
  • Default value: ""
nand_spare_image_filename

Name of the NAND spare image to load into the NAND memory model of the board component. The supported format is raw binary (.bin or .craff).

  • Range: File name string.
  • Default value: ""
qspi_image_filename

Name of the QSPI image to load into the QSPI memory model of the board component. The supported format is raw binary (.bin or .craff).

  • Range: File name string.
  • Default value: ""
usb3_image_filename

Name of the USB disk image that corresponds to the SuperSpeed disk in the board component connected to the USB 3.1 controller. The image file must be smaller or equal than the disk size.

The supported format is .craff, .img or .wic.

  • Range: File name string.
  • Default value: ""
usb3_hs_image_filename

Name of the USB disk image that corresponds to the high-speed disk in the board component connected to the USB 3.1 controller. The image file must be smaller or equal than the disk size.

The supported format is .craff, .img or .wic.

  • Range: File name string.
  • Default value: ""
usb_otg_image_filename

Name of the USB disk image that corresponds to the high-speed disk in the board component connected to the USB 2.0 OTG controller. The image file must be smaller or equal than the disk size.

The supported format is .craff, .img or .wic.

  • Range: File name string.
  • Default value: ""
hps_cpu_freq_mhz ARM cores frequency in Megahertz (MHz).
  • Range: Integer between 400 and 1500
  • Default value: 400 MHz
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