Intel® Simics® Simulator for Intel® FPGAs: Intel Agilex® 5 E-Series Virtual Platform User Guide

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ID 786901
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About This Document 2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms 3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model 5. Supported Use Cases A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms x
2.1. Intel Agilex® 5 E-Series Universal Virtual Platform
2.1. Intel Agilex® 5 E-Series Universal Virtual Platform x
2.1.1. Intel Agilex® 5 E-Series Universal Virtual Platform Overview 2.1.2. Intel Agilex® 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.1.3. Intel Agilex® 5 E-Series Virtual Platform Key Capabilities
2.1.1. Intel Agilex® 5 E-Series Universal Virtual Platform Overview x
2.1.1.1. Intel Agilex® 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Intel Agilex® 5 E-Series Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges
3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components
3.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model x
3.1.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Intel Agilex® 5 E-Series HPS Components
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Intel Agilex® 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms
3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model
5. Supported Use Cases
A. Document Revision History

4.4. Getting Device Information from the Intel® Simics® Model

List the devices in an Intel® Simics® model with the devs Intel® Simics® CLI command. Only devices mapped in a memory space are listed with the command. The devs command also displays the memory space and memory map for each device. The following example shows the truncated output from running the devs Intel® Simics® CLI command: 

# Intel Simics simulator CLI 

running> devs
--------------------------------------------------------------------------------
Count      Device              Space                 Range            Fn/Port
--------------------------------------------------------------------------------
0     system.board.fpga   system.board.fpga    0x0000000000000000 -  memory_bank
      .soc_inst.example   .soc_inst.example    0x00000000000fffff
      design.design       _design.design_mem
      _memory

0     system.board.fpga   system.board.fpga    0x000000001c000000 -   0
      .soc_inst.hps_      .soc_inst.hps_       0x000000001c000fff
      subsys.agilex_hps   subsys.agilex_hps                                  
      .ccu.bank.caiu0     .phys_mem

0     system.board.fpga   system.board.fpga    0x000000001c005000 -   0
      .soc_inst.periph_   .soc_inst.hps_       0x000000001c005fff
      subsys.example_     subsys.agilex_
      design_lw.design    hps.phys_mem
      _memory
:
:
:

0     system.board.fpga.  system.board.fpga    0x0000000010a30000 -   0
      soc_inst.hps_       .soc_inst.hps_       0x0000000010a304ff
      subsys.sdm.sdm      subsys.agilex_hps
      _mailbox.bank.regs  .phys_mem

0     system.board.fpga   system.board.fpga    0x0000000000000000 -   memory_bank
      .soc_inst.periph_   .soc_inst.periph_    0x00000000000fffff
      subsys.example_     subsys.example_
      design_lw.design    design_lw.design
      _memory            _mem
---------------------------------------------------------------------------------

The table shows the path of the devices. The device paths depend on the virtual model. The paths shown correspond to those you see using the Intel Agilex® 5 E-Series Universal Virtual Platform.

To get device information for a single device, run the devs Intel® Simics® CLI command with the device path information obtained earlier. For example, the devs system.board.fpga.soc_inst.hps_subsys.agilex_hps.pwrmgr.bank.regs command returns a table like the following table: 
#Intel Simics simulator CLI 

simics> devs system.board.fpga.soc_inst.hps_subsys.agilex_hps.pwrmgr.bank.regs
-------------------------------------------------------------------
Count       Device                Space             Range	  Fn
-------------------------------------------------------------------
0      system.board.fpga    system.board.fpga    0x10d14000 -   0
       .soc_inst.hps_       .soc_inst.hps_       0x10d1405b
       subsys.agilex_hps.   subsys.agilex_hps
       pwrmgr.bank.regs     .phys_mem
-------------------------------------------------------------------

Examine the registers of a specific device and the current value of them with the print-device-regs Intel® Simics® CLI command. Provide the path of the device register banks (as found with the devs command) as a parameter. For example, the print-device-regs system.board.fpga.soc_inst.hps_subsys.agilex_hps.pwrmgr.bank.regs command returns the following information: 

#Intel Simics simulator CLI 

simics> print-device-regs system.board.fpga.soc_inst.hps_subsys.agilex_hps.pwrmgr.bank.regs
--------------------------------------+-----------------------------------------
Offset  Name             Size    Value| Offset  Name               Size  Value
--------------------------------------+-----------------------------------------
   0x0  DSU_FWENCTL         4     0x0 |   0x30  FSM_CPUx_PWRCTLR[3] 4    0x0
   0x4  DSU_PGENCTL         4     0x0 |   0x34  FSM_CPUx_PWRSTAT[3] 4    0x0
   0x8  DSU_PGSTAT          4     0x0 |   0x38  APS_FWENCTL         4    0x0
   0xc  FSM_DSU_PWRCTLR     4     0x0 |   0x3c  APS_PGENCTL         4    0x0
  0x10  FSM_DSU_PWRSTAT     4     0x0 |   0x40  APS_PGSTAT          4    0x0
  0x14  DSU_PWRSTAT         4     0x0 |   0x44  PSS_FWENCTL         4    0x0
  0x18  FSM_CPUx_PWRCTLR[0] 4     0x0 |   0x48  PSS_PGENCTL         4    0x0
  0x1c  FSM_CPUx_PWRSTAT[0] 4     0x0 |   0x4c  PSS_PGSTAT          4    0x0
  0x20  FSM_CPUx_PWRCTLR[1] 4     0x0 |   0x50  MPU_PCHCTLR         4    0x1
  0x24  FSM_CPUx_PWRSTAT[1] 4     0x0 |   0x54  MPU_PCHSTAT         4    0x0
  0x28  FSM_CPUx_PWRCTLR[2] 4     0x0 |   0x58  MPU_BOOTCONFIG      4  0x303
  0x2c  FSM_CPUx_PWRSTAT[2] 4     0x0 |                                         
--------------------------------------------------------------------------------

You also can list the object below a specific hierarchy in a virtual platform using the list-objects Intel® Simics® CLI command. In addition to listing the objects, this command indicates the class to which each object belongs.

This information is beneficial when analyzing the components in a virtual platform. The following output is an example of the list-objects command output showing the objects in the board component: 

# Intel Simics simulator CLI 
simics> list-objects namespace = system.board
-----------------------------------------------------
    Component Class                 Object
-----------------------------------------------------
<AT24Cxx_comp>              system.board.eeprom_16b_0
    :                                 :                   
<AT24Cxx_comp>              system.board.eeprom_8b_4
<sm_universal_fpga_comp>    system.board.fpga
<i2c_link_v2>               system.board.i2c_bus_0
<i2c_link_v2>               system.board.i2c_bus_1
<i2c_link_v2>               system.board.i2c_bus_2
<i2c_link_v2>               system.board.i2c_bus_3
<i2c_link_v2>               system.board.i2c_bus_4
    :                                 :
<sm_hps_nand_flash_comp>    system.board.nand
<spi_flash_comp>            system.board.qspi
<sd_comp>                   system.board.sd_card
<spi_flash_comp>            system.board.spi_flash
-----------------------------------------------------

-----------------------------------------
   Class                  Object
-----------------------------------------
<connector>      system.board.eth0
<connector>      system.board.eth1
<connector>      system.board.eth2
<marvell_phy>    system.board.phy0
<connector>      system.board.phy0_slot
<marvell_phy>    system.board.phy1
<connector>      system.board.phy1_slot
<marvell_phy>    system.board.phy2
<connector>      system.board.phy2_slot
-----------------------------------------
Remember: The device path information depends on the virtual platform that you use during simulation. The paths here are from the Intel Agilex® 5 E-Series HPS model in the Intel Agilex® 5 E-Series Universal Virtual Platform. The paths in the Intel Agilex® 5 E-Series Intel® Simics® model follow the system.board.fpga hierarchy approach described in Understanding Target Scripts in Intel® Simics® Simulator for Intel® FPGAs User Guide.
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