Intel® Simics® Simulator for Intel® FPGAs: Intel Agilex® 5 E-Series Virtual Platform User Guide

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ID 786901
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About This Document 2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms 3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model 5. Supported Use Cases A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms x
2.1. Intel Agilex® 5 E-Series Universal Virtual Platform
2.1. Intel Agilex® 5 E-Series Universal Virtual Platform x
2.1.1. Intel Agilex® 5 E-Series Universal Virtual Platform Overview 2.1.2. Intel Agilex® 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.1.3. Intel Agilex® 5 E-Series Virtual Platform Key Capabilities
2.1.1. Intel Agilex® 5 E-Series Universal Virtual Platform Overview x
2.1.1.1. Intel Agilex® 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Intel Agilex® 5 E-Series Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges
3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components
3.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model x
3.1.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Intel Agilex® 5 E-Series HPS Components
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Intel Agilex® 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms
3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model
5. Supported Use Cases
A. Document Revision History

2.1.1.1. Intel Agilex® 5 HPS Component

The Intel Agilex® 5 HPS component in the virtual platform is an Intel® Simics® model that corresponds to the Hard Processor System Intel Agilex® 5 FPGA IP in the Intel® Quartus® Prime software. The hierarchical name of the HPS component in the virtual platform is system.board.fpga.soc_inst.hps_subsys.agilex_hps.

Note: An alias for this component is created to facilitate the access to this component from the Intel® Simics® simulator CLI using just the hps accessor.

The HPS component consists of the following main functional blocks:

  • MPU Subsystem: The HPS component includes a HPS microprocessor unit (MPU) model. The MPU in the Intel Agilex® 5 E-Series SoC FPGA HPS consists of two Arm* Cortex* -A55 cores and two Arm* Cortex* -A76 cores.

    The model of the cores executes the HPS embedded software binaries, and the execution of these binaries directs the simulation flow. You can adjust the parameters of the HPS component to select the boot core to use and the power state of each core, similar to the settings you have in the HPS IP in Intel® Quartus® Prime software. These parameters are defined in the target script that configures the Intel® Simics® HPS model.

  • OCRAM: The on-chip RAM (OCRAM) in the HPS is the initial boot device for the HPS.

    In hardware, the first stage bootloader is provided as part of the bitstream which the SDM consumes. The SDM loads the bootloader into the OCRAM and takes the HPS out from reset so the HPS can start executing the bootloader code. Because the Intel Agilex® 5 E-Series Universal Virtual Platform does not fully model configuration, the image of the first stage bootloader is loaded directly into the OCRAM. The target script specifies the path of the first-stage bootloader image as a parameter.

  • Flash Controllers: The binaries to be executed by the HPS are stored in a flash device. The flash device can be a NAND memory, an SD card, or a QSPI memory.

    To access these flash devices, the software running on the boot core uses the flash controllers to read the next boot stage software binaries from the flash device and load them into the SDRAM. The Intel® Simics® model of the flash memory devices is part of the board component. A board component can supply an image to be loaded into that flash device. The image is defined as a user-configurable parameter provided as part of the target script.

    Note: In the Intel® Simics® model of the Combo PHY, the interface between the SD card/NAND flash device and the corresponding host controller is performed at the transaction level through API calls rather than a physical level.
  • UART Controller: The Intel® Simics® simulator includes a serial console that you can use to interact with the software running on the target system. To enable the serial console, the HPS component of the Intel® Simics® model includes an Intel® Simics® model of the UART controller. Use the Intel® Simics® Serial console connected to the UART to view messages created by the software running in the HPS and provide input to the U-Boot or Linux prompt. The serial console is created by default in the target script, but you can also disable it through a target script parameter.
  • Ethernet Media Access Controller (MAC): The virtual platform supports Ethernet connectivity using the TSN controller, enabling eth0 Ethernet link.

    In the virtual platform, an Intel® Simics® service node component provides network services in the simulated target system and provides connectivity between the host machine and the target system. The service node is instantiated as part of the target script. The Ethernet media access controller (MAC) interfaces with the service node through the Intel® Simics® models of the Ethernet marvel PHY device and an Ethernet port. Both are instantiated as part of the board component. Several kinds of connection between the simulated network and the physical ("real") host network are supported in Intel® Simics® .

    For more information about networking capabilities in Intel® Simics® simulations, refer to Networking with the Simulated Target System in the Intel® Simics® Simulator for Intel® FPGAs User Guide.

  • General Purpose I/O (GPIO) Interface: The virtual platform supports GPIO functionality through the GPIO0 and GPIO1 ports modeled as part of the HPS Intel® Simics® model. These ports allow the GPIO pins to be configured as input or output.

    There are use-cases and applications that make use of these ports that allow some interaction with board-level components. The Intel Agilex® 5 E-Series Universal Virtual Platform also offers a GPIO loopback model in which pairs of pins are tied together to emulate a loopback configuration. The loopback support is provided as part of the board component.

  • HPS-to-FPGA Bridges: The virtual platform implements an example design connected to the HPS-to-FPGA bridges, which is an Intel® Simics® model of an On-Chip Memory IP.

    There are two instances of this example design connected to the HPS2FPGA and LWHPS2FPGA bridges (each instance is connected to one of the bridges). Software running in the HPS can access the memory devices in the fabric example design by accessing the memory address range in which these are mapped under the FPGA component.

  • FPGA-to-HPS Bridges: The virtual platform includes a few bridges that connect the FPGA logic with the HPS (FPGA2HPS) and the SDRAM (FPGA2SDRAM). Under the FPGA logic, few memory spaces were created that are used as an initiator for write and read operations to the HPS and SDRAM components.
  • I2C and I3C Controllers: You can configure them as hosts accessing the I2C or I3C devices connected to the buses. The I3C controller also supports connecting legacy I2C devices.

    The type of devices that can be connected to the bus are smart sensors and flash memories such as EEPROM. The I3C controller can be configured as a host or target device. Several instances of the controllers are implemented in this virtual platform to match real hardware architecture. All the instances of the I2C controller are used as general-purpose I2C controllers. While I2C controllers in real hardware can be used as a control interface for Ethernet transceivers, using I2C controllers is not supported in this virtual platform.

  • USB Controllers: Two USB controllers that operate in host mode (USB 2.0 OTG and USB 3.1 Gen 1) are supported. The controllers offer the following features:
    • Support hot plug (plug and unplug) during simulation
    • Allow access to mass storage devices

    The USB 3.1 Gen 1 controller provides host functions to access high-speed and super-speed devices and does not support being configured in device mode. The USB 2.0 OTG supports a single USB port connected through a USB 2.0 transceiver with high-speed devices.

  • SPI Controller: Two instances of the SPI IP are configured as host (SSI HOST) and two instances as target (SSI_DEVICE), enabling serial communication with any SPI board device. These devices can be flash memories, EEPROMs, or sensors.
  • Power Manager: Supports powering on the user-defined boot core. You can select the combination of CPU cores to use in the application using the target script and emulate the settings coming from bitstream. Similar to hardware behavior, these settings are static and cannot be changed later in the simulation. Only core 0 and core 2 can be configured as boot core.
  • Reset Manager: Supports a number of different HPS reset types, such as cold reset, warm reset, and watchdog timer reset, handling the reset sequence flow for each one of these resets.
  • System Manager: Contains logic to control system functions and other modules that need external control signals provided as part of system integration.
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