Intel® Simics® Simulator for Intel® FPGAs: Intel Agilex® 5 E-Series Virtual Platform User Guide

Download PDF
ID 786901
Date 12/04/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About This Document 2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms 3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model 5. Supported Use Cases A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms x
2.1. Intel Agilex® 5 E-Series Universal Virtual Platform
2.1. Intel Agilex® 5 E-Series Universal Virtual Platform x
2.1.1. Intel Agilex® 5 E-Series Universal Virtual Platform Overview 2.1.2. Intel Agilex® 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.1.3. Intel Agilex® 5 E-Series Virtual Platform Key Capabilities
2.1.1. Intel Agilex® 5 E-Series Universal Virtual Platform Overview x
2.1.1.1. Intel Agilex® 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Intel Agilex® 5 E-Series Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges
3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components
3.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model x
3.1.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Intel Agilex® 5 E-Series HPS Components
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric Peripheral Subsystem On-Chip Memory Example Design FPGA-To-HPS Bridge Memory Spaces
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Intel Agilex® 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms
3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model
5. Supported Use Cases
A. Document Revision History

3.3.1. FPGA Fabric

Three components integrate the FPGA fabric model:

  • Peripheral subsystem
  • On-Chip memory example design
  • FPGA-To-HPS Bridge memory spaces

The following sections provide additional details about these components:

Peripheral Subsystem

The peripheral subsystem only includes an FPGA fabric example design instance, which consists of an On-chip memory IP. This memory is connected to the HPS through the lwhps2fpga bridge. For more information about this model, refer to the On-Chip Memory Example Design section.

On-Chip Memory Example Design

The On-Chip memory IP allows read/write operations from/to the HPS software connected through the hps2fpga bridge.
  • An instance of the On-Chip memory is instantiated directly under the qsys_top component and is connected with the HPS through the hps2fpga bridge (example_design).
  • The second instance of the On-Chip memory is instantiated under the peripheral sub-system (also instantiated under the qsys_top component) and is connected with the HPS through the lwhps2fpga bridge (example_design_lw).

The mapping of the memory instances is defined as follows:

Example Design Name

Bridge

Size

Start Address

End Address
example_design

hps2fpga

1 MB

0x0040000000

0x00400FFFFF

example_design_lw

lwhps2fpga

1 MB

0x0020000000

0x00200FFFFF

The example design instances in the FPGA fabric receive a parameter named base_addr that defines an offset value that indicates the mapping of the instance, taking as reference the Start Address value defined in the previous table.

The objects corresponding to the example design are the following:

  • system.board.fpga.soc_inst.example_design
  • system.board.fpga.soc_inst.periph_subsys.example_design_lw

FPGA-To-HPS Bridge Memory Spaces

Initiators in the FPGA logic model use these memory spaces to start read/write operations directed to the HPS or SDRAM components.

Level Two Title