Intel® Simics® Simulator for Intel® FPGAs: Intel Agilex® 5 E-Series Virtual Platform User Guide

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ID 786901
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About This Document 2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms 3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model 5. Supported Use Cases A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms x
2.1. Intel Agilex® 5 E-Series Universal Virtual Platform
2.1. Intel Agilex® 5 E-Series Universal Virtual Platform x
2.1.1. Intel Agilex® 5 E-Series Universal Virtual Platform Overview 2.1.2. Intel Agilex® 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.1.3. Intel Agilex® 5 E-Series Virtual Platform Key Capabilities
2.1.1. Intel Agilex® 5 E-Series Universal Virtual Platform Overview x
2.1.1.1. Intel Agilex® 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Intel Agilex® 5 E-Series Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges
3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components
3.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model x
3.1.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Intel Agilex® 5 E-Series HPS Components
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Intel Agilex® 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms
3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model
5. Supported Use Cases
A. Document Revision History

2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design

Two instances of the On-Chip memory design exist in the FPGA fabric model. One of these instances is located directly under the qsys_top component, while the other resides under the peripheral subsystem. Each one of the On-Chip memory instances has a size of 1 MB and is connected to the HPS2FPGA bridges. This On-Chip memory model supports reading and writing to any memory location.

You can access the memory designs using direct memory access to the memory locations in which these are mapped under the HPS2FPGA bridges memory space or by accessing the memories example design as a memory space.

Read from example design memory space: 

system.board.fpga.soc_inst.example_design.design_mem.read <addr loc>
system.board.fpga.soc_inst.periph_subsys.example_design_lw.design_mem.read <addr loc>

Write to example design memory space: 

system.board.fpga.soc_inst.example_design.design_mem.write <addr loc> <value>
system.board.fpga.soc_inst.periph_subsys.example_design_lw.design_mem.write <addr loc> <value>

The following commands read and write a 32-bit word into the specified address location on the example design (from 0 to 1MB) using the corresponding HPS2FPGA base address. The HPS software must follow this approach when accessing the example design:

Read from example design using HPS2FPGA address: 

system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.get <0x40000000 +addr loc>
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.get <0x20000000 +addr loc>

Write to example design using HPS2FPGA address: 

system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.set <0x40000000 +addr loc> <value>
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.set <0x20000000 +addr loc> <value>

Adjust addresses based on the value set in the base_addr parameter in the example design. The address to use in Intel® Simics® commands depends on the value assigned to the base_addr parameter.

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