Intel® Simics® Simulator for Intel® FPGAs: Intel Agilex® 5 E-Series Virtual Platform User Guide

ID 786901
Date 12/04/2023
Public

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2.1.3.5. General Purpose I/O (GPIO) Loopback

The virtual platform supports a model that creates a loopback connection in certain pins in GPIO0 and GPIO1 ports. This feature is implemented at board component level.

The loopback implementation consists of directly connecting GPIO in and out pins of the GPIO ports in both directions to reflect the same state on those pins.

In each GPIO port, the following pairs of pins are connected as shown in the image below:

  • [0,1]
  • [5,6]
  • [18,19]
  • [20,21]
Figure 6. General Purpose I/O (GPIO) Loopback