F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 720985
Date 4/18/2024
Public
Document Table of Contents

6.8.1. XGMII TX Signals

Table 28.  XGMII Transmit Signals
Signal Condition Direction Width Description
xgmii_tx_data[]

Use legacy Ethernet 10G MAC XGMII interface disabled.

Out 32

4-lane data bus. Lane 0 starts from the least significant bit.

  • Lane 0: xgmii_tx_data[7:0]
  • Lane 1: xgmii_tx_data[15:8]
  • Lane 2: xgmii_tx_data[23:16]
  • Lane 3: xgmii_tx_data[31:24]
xgmii_tx_control[]

Use legacy Ethernet 10G MAC XGMII interface disabled.

Out 4

Control bits for each lane in xgmii_tx_data[].

  • Lane 0: xgmii_tx_control[0]
  • Lane 1: xgmii_tx_control[1]
  • Lane 2: xgmii_tx_control[2]
  • Lane 3: xgmii_tx_control[3]
xgmii_tx_valid

Use legacy Ethernet 10G MAC XGMII interface disabled.

Out 1 XGMII TX valid signal. When asserted, indicates that the data and control buses are valid.