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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP User Guide Archives
9. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition)
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
6.1. Clock and Reset Signals
6.2. Speed Selection Signal
6.3. Error Correction Signals
6.4. Avalon® Memory-Mapped Interface Programming Signals
6.5. Avalon® Streaming Data Interfaces
6.6. Avalon® Streaming Flow Control Signals
6.7. Avalon® Streaming Status Interface
6.8. PHY-side Interfaces
6.9. IEEE 1588v2 Interfaces
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6.4. Avalon® Memory-Mapped Interface Programming Signals
Signal | Direction | Width | Description |
---|---|---|---|
csr_address[] | In | 10/13 | Use this bus to specify the register address to read from or write to. The width is 13 bits when you enable the Use Legacy Ethernet 10G MAC Avalon® memory-mapped interface option. |
csr_read | In | 1 | Assert this signal to request a read. |
csr_readdata[] | Out | 32 | Data read from the specified register. The data is valid when thecsr_waitrequest signal is deasserted. |
csr_write | In | 1 | Assert this signal to request a write. |
csr_writedata[] | In | 32 | Data to be written to the specified register. The data is written when the csr_waitrequest signal is deasserted. |
csr_waitrequest | Out | 1 | When asserted, this signal indicates that the MAC IP core is busy and not ready to accept any read or write requests.
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