Visible to Intel only — GUID: luq1663006364913
Ixiasoft
Visible to Intel only — GUID: luq1663006364913
Ixiasoft
8.3. Test Configurations
The design example supports nine configurations as shown in the following figure.
Descriptions of each of these configurations are shown in the table shown below:
Configuration Name | Encryption Algorithm | Traffic Pattern | Key Size | Interleaving |
---|---|---|---|---|
AES GCM Profile, 256-bit Key | AES | GCM | 256 bits | Frame-based |
AES MACSec Profile, 256-bit Key | AES | MACSec | 256 bits | Frame-based |
AES IPSec Profile, 256-bit Key | AES | IPSec | 256 bits | Frame-based |
AES XTS Profile, 2 X 256-bit Keys | AES | XTS | 512 bits (2 X 256 bit keys) | Frame-based |
SM4 GCM Profile, 128-bit Key | SM4 | GCM | 128 bits | Frame-based |
AES MACSec and GCM, Cycle-Based Interleave | AES | MACSec and GCM | 256 bits | Cycle-based |
AES MACSec and GCM, Frame-Based Interleave | AES | MACSec and GCM | 256 bits | Frame-based |
AES XTS and GCM, Cycle-Based Interleave | AES | XTS and GCM | 256 bits; 512 bits (2 X 256 bit keys) for XTS | Cycle-based |
AES XTS and GCM, Frame-Based Interleave | AES | XTS and GCM | 256 bits; 512 bits (2 X 256 bit keys) for XTS | Frame-based |
When the example design is generated, several directories and files are created as shown below:
The example.ip file is created when the example design is generated. The name of this file is always example.ip although the directory location for this file can be specified in the Symmetric Cryptographic Intel FPGA Hard IP GUI. This is a Platform Designer .ip file that specifies an instance of the crypto_hip_agx IP along with default parameter settings.
The files example_design.qpf and example_design.qsf are a Quartus project file and a Quartus project settings file respectively that can be used to synthesize the example design. This process is described in a later section.
The next two directory levels are example/ and example_design/.
The example/ directory looks like the following:
The crypto_hip_agx_120/ directory contains the simulation and synthesis RTL files for the crypto_hip_agx example instance. The sim/ directory contains the simulation scripts for the various simulators.
The example_design/ directory contains the remainder of the example design files including the VSIP RTL, the testbench for simulation, and the test description files.