Symmetric Cryptographic Intel FPGA Hard IP User Guide

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ID 714305
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Cryptographic IP Data Profiles 7. Configuration Registers 8. Design Example 9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives 10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
1. Introduction x
1.1. Terminology 1.2. IP Core Overview 1.3. Release Information 1.4. Device Family Support 1.5. Resource Utilization
1.2. IP Core Overview x
1.2.1. IP Core Applications
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. AXI-ST Interface 2.4. AXI-Lite Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Symmetric Cryptographic IP Core Flow 4.5. Dynamically Disabling SM4 Capability 4.6. Error Handling 4.7. Error Reporting 4.8. Resetting the IP Core 4.9. Channel Definition and Allocation 4.10. Byte Ordering 4.11. AXI-ST Single Packet Mode 4.12. AXI-ST Multiple Packet Mode
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.6. Error Handling x
4.6.1. Detected Error Handling 4.6.2. Key RAM ECC Error Handling
5. Block Description x
5.1. Reset Sequencer 5.2. AXI-ST Ready Latency 5.3. AXI Adapter 5.4. Integrity Check Value Comparison 5.5. GCM Padding and Depadding
5.3. AXI Adapter x
5.3.1. MAC Packing 5.3.2. Data Last Indicator 5.3.3. Stream and Channel ID Buffering 5.3.4. TKEEP and LAST_SEGMENT Signals Generation 5.3.5. MAC Dropping on Decryption
5.5. GCM Padding and Depadding x
5.5.1. GCM Padding 5.5.2. GCM Depadding
6. Cryptographic IP Data Profiles x
6.1. MAC Security Profile (MACsec) 6.2. IP Security Profile (IPsec) 6.3. Generic GCM Profile (GCM) 6.4. Generic XTS Profile (XTS)
6.1. MAC Security Profile (MACsec) x
6.1.1. MACsec Flow 6.1.2. AXI-ST Interface Using MAC Security (MACsec) Profile Pattern
6.2. IP Security Profile (IPsec) x
6.2.1. AXI-ST Interface Using IP Security (IPsec) Profile Pattern
6.3. Generic GCM Profile (GCM) x
6.3.1. AXI- ST Interface Using Generic GCM Profile Pattern
6.4. Generic XTS Profile (XTS) x
6.4.1. AXI-ST Interface Using Generic XTS Profile Pattern
8. Design Example x
8.1. Functional Description 8.2. Crypto VSIP Top Block Descriptions 8.3. Test Configurations 8.4. Software Requirements 8.5. Simulation Requirements 8.6. Steps to Generate the Design Example 8.7. Running Simulation Tests 8.8. Running Hardware Tests
8.2. Crypto VSIP Top Block Descriptions x
8.2.1. Clock and Reset 8.2.2. Host Interface
8.7. Running Simulation Tests x
8.7.1. Steps to Simulate the Design Example
8.8. Running Hardware Tests x
8.8.1. Supported Boards 8.8.2. Steps to Compile the Design Example for Hardware 8.8.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide

8.3. Test Configurations

The design example supports nine configurations as shown in the following figure.

Figure 31. Supported Design Configurations

Descriptions of each of these configurations are shown in the table shown below:

Table 43.  Descriptions of Supported Configurations
Configuration Name Encryption Algorithm Traffic Pattern Key Size Interleaving
AES GCM Profile, 256-bit Key AES GCM 256 bits Frame-based
AES MACSec Profile, 256-bit Key AES MACSec 256 bits Frame-based
AES IPSec Profile, 256-bit Key AES IPSec 256 bits Frame-based
AES XTS Profile, 2 X 256-bit Keys AES XTS 512 bits (2 X 256 bit keys) Frame-based
SM4 GCM Profile, 128-bit Key SM4 GCM 128 bits Frame-based
AES MACSec and GCM, Cycle-Based Interleave AES MACSec and GCM 256 bits Cycle-based
AES MACSec and GCM, Frame-Based Interleave AES MACSec and GCM 256 bits Frame-based
AES XTS and GCM, Cycle-Based Interleave AES XTS and GCM 256 bits; 512 bits (2 X 256 bit keys) for XTS Cycle-based
AES XTS and GCM, Frame-Based Interleave AES XTS and GCM 256 bits; 512 bits (2 X 256 bit keys) for XTS Frame-based

When the example design is generated, several directories and files are created as shown below:

Figure 32. Example Design Directory Tree

The example.ip file is created when the example design is generated. The name of this file is always example.ip although the directory location for this file can be specified in the Symmetric Cryptographic Intel FPGA Hard IP GUI. This is a Platform Designer .ip file that specifies an instance of the crypto_hip_agx IP along with default parameter settings.

The files example_design.qpf and example_design.qsf are a Quartus project file and a Quartus project settings file respectively that can be used to synthesize the example design. This process is described in a later section.

The next two directory levels are example/ and example_design/.

The example/ directory looks like the following:

Figure 33. Example Directory from Design Example Generation

The crypto_hip_agx_120/ directory contains the simulation and synthesis RTL files for the crypto_hip_agx example instance. The sim/ directory contains the simulation scripts for the various simulators.

Note: The Aldec simulation script is not supported at this time.

The example_design/ directory contains the remainder of the example design files including the VSIP RTL, the testbench for simulation, and the test description files.

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