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1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores
4.2. Specifying the IP Core Parameters and Options
4.3. Generated File Structure
4.4. Symmetric Cryptographic IP Core Flow
4.5. Dynamically Disabling SM4 Capability
4.6. Error Handling
4.7. Error Reporting
4.8. Resetting the IP Core
4.9. Channel Definition and Allocation
4.10. Byte Ordering
4.11. AXI-ST Single Packet Mode
4.12. AXI-ST Multiple Packet Mode
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5.2. AXI-ST Ready Latency
The Symmetric Cryptographic IP core implements the AXI-ST ready latency on the AXI-ST TX ingress responder. The supported range of ready latency is 0 to 15.
Figure 11. AXI-ST Ready Latency Signals
Note: The AXI-ST RX egress port always operates with a ready latency of 0 and complies with the AXI specification.