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Ixiasoft
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores
4.2. Specifying the IP Core Parameters and Options
4.3. Generated File Structure
4.4. Symmetric Cryptographic IP Core Flow
4.5. Dynamically Disabling SM4 Capability
4.6. Error Handling
4.7. Error Reporting
4.8. Resetting the IP Core
4.9. Channel Definition and Allocation
4.10. Byte Ordering
4.11. AXI-ST Single Packet Mode
4.12. AXI-ST Multiple Packet Mode
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Ixiasoft
1.5. Resource Utilization
Device | Variant | ALM | M20K |
---|---|---|---|
AGFC023R25A2E2V |
|
6,855 1 | 124 |
|
5,1851 | 53 |
Fabric Speed Grade | app_ip_st_clk Fmax | Theoretical Throughput |
-1 | 460Mhz | 260Gbps |
-2 | 400Mhz | 200Gbps |
-3 | 380Mhz | 190Gbps |
1 ALM usage can increase up to 10% with higher FPGA utilization. ALM usage also increases if you add ready latency on AXI interfaces.