2.3. AXI-ST Interface
Port Name | Width (Bits) | Direction | Description |
---|---|---|---|
app_ip_st_clk | 1 | Input | AXI-ST interface input clock signal |
app_ip_st_areset_n | 1 | Input | AXI-ST interface virtual port. Reserved for future use. |
Port Name | Width (Bits) | Direction | Description |
---|---|---|---|
p0_app_ip_tx_tvalid | 1 | Input | AXI-ST valid signal. When asserted, indicates that the TX operation is valid. |
p0_ip_app_tx_tready | 1 | Output | AXI-ST ready signal. |
p0_ip_app_tx_tid | 32 | Input | Indicates the transaction ID (TID). The signal is valid on every transfer of the packet.
Note: The stream ID is available for MACsec only.
|
p0_app_ip_tx_tdata | 512 | Input | Indicates the TX data. |
p0_app_ip_tx_tkeep | 64 | Input | Indicates the type of data byte:
Note: The null byte is available at the end of the transfer only. Not available during the beginning or in a middle of the transfer.
|
p0_app_ip_tx_tlast | 1 | Input | Indicates the last data and end of the transfer. |
p0_app_ip_tx_tuser | 138 | Input | 138-bit bus indicating pattern-specific information.
|
p0_app_ip_tx_tuser_last_ segment<seg-num> | 1 | Input | Indicates the packet segmentation boundary for higher bandwidth transfer, applicable for MACsec and IPsec profiles:
|
Port Name | Bit Mapping to p0_app_ip_ tx_tuser [137:0] | Direction | Description |
---|---|---|---|
p0_app_ip_tx_tuser.algorithm_types | 0 | Input | Indicates the mode for the current clock cycle.
|
p0_app_ip_tx_tuser.encrypt_decrypt | 1 | Input | Indicates the encrypt or decrypt mode for the current clock cycle.
|
p0_app_ip_tx_tuser.key_128b_256b | 2 | Input | Indicates the key size for the current clock cycle.
|
p0_app_ip_tx_tuser.pattern[2:0] | 5:3 | Input | Indicates the encoding for the traffic pattern type.
|
p0_app_ip_tx_tuser.mac_iv_tweak_en | 6 | Input | Indicates that the data fields carry an IV or a tweak value for the XTS mode. |
p0_app_ip_tx_tuser.data_en | 7 | Input | Indicates that for a given pattern ID, the data bits carry the raw data into the cryptographic IP core. |
p0_app_ip_tx_tuser.key_en | 8 | Input | Indicates that the data carries the keys. |
p0_app_ip_tx_tuser.auth_tag[127:0] | 136:9 | Input | Indicates the Integrity Check Value (ICV) field on the decryption packet. |
p0_app_ip_tx_tuser.error_clear | 137 | Input | When set, the IP core resets the internal error indicated by the profile ID and the channel ID associated with this clock. Resetting the error allows usage of the profile and channel again.
Note: You should make the "error_clear" cycle a standalone transaction with the intended profile, stream, or channel values. You should not mix this transaction with a key or data cycle. Don't mix error_clear with a key_en, iv_tweak_en or otherwise they are ignored once error_clear is set.
|
Port Name | Width (Bits) | Direction | Description |
---|---|---|---|
p0_app_ip_rx_tvalid | 1 | Output | AXI-ST valid signal. When asserted, indicates that the RX operation is valid. |
p0_ip_app_rx_tready | 1 | Input | AXI-ST ready signal. |
p0_ip_app_rx_tid | 32 | Output | Indicates the transaction ID (TID). The signal is valid on every transfer of the packet.
Note: The stream ID is available for MACsec only.
|
p0_app_ip_rx_tdata | 512 | Output | Indicates the RX data. |
p0_app_ip_rx_tkeep | 64 | Output | Indicates the type of data byte:
Note: The null byte is available at the end of the transfer only. Not available during the beginning or in a middle of the transfer.
|
p0_app_ip_rx_tlast | 1 | Output | Indicates the last data and end of the transfer. |
p0_app_ip_rx_tuser | 17 | Output | 17-bit bus indicating pattern-specific information.
|
p0_app_ip_rx_tuser_ last_segment<seg-num> | 1 | Output | Indicates the packet segmentation boundary for higher bandwidth transfer:
|
Port Name | Bit Mapping to p0_app_ip_ rx_tuser [16:0] | Direction | Description |
---|---|---|---|
p0_app_ip_rx_tuser.algorithm_types | 0 | Output | Indicates the mode for the current clock cycle.
|
p0_app_ip_rx_tuser.encrypt_decrypt | 1 | Input | Indicates the encrypt or decrypt mode for the current clock cycle.
|
p0_app_ip_rx_tuser.key_128b_256b | 2 | Output | Indicates the key size for the current clock cycle.
|
p0_app_ip_rx_tuser.pattern[2:0] | 5:3 | Output | Indicates the encoding for the traffic pattern type.
|
p0_app_ip_rx_tuser.mac_iv_tweak_en | 6 | Output | Indicates that the data fields carry an IV or a tweak value for the XTS mode. |
p0_app_ip_rx_tuser.data_en | 7 | Output | Indicates that for a given pattern ID, the data bits carry the raw data out of the cryptographic IP cores. |
p0_app_ip_rx_tuser.next_packet_en | 8 | Output | Indicates that a start of a new packet occurs midway through the data lines. Only valid signal when the tlast signal asserts in the same clock as the tkeep signal. |
p0_ip_app_rx_tuser.error_status | 9 | Output | Indicates any error relative to the inputs. This signal is valid when tvalid is set to 1.
|
p0_ip_app_rx_tuser.error_code[4:0] | 14:10 | Output | Indicates the error code for the current cycle. This signal is valid when tvalid is set to 1 and error_status is set to 1. |
p0_ip_app_rx_tuser.auth_error | 15 | Output | Indicates whether an integrity check error occurs during the packet decryption. This signal is valid when tlast is asserted. |
p0_ip_app_rx_tuser.internal_error | 16 | Output | Indicates that an internal error was detected. This signal is synchronous to app_ip_st_clk but it is not always aligned to rx_tvalid, depending on the occurrence of the error. When asserted, it requires you to read the error status code and the CSR to determine the error. You must ensure the error_clear bit is set with the correct profile, stream and channel ID of the error in order to use the Cryptographic IP again for that profile and channel. |