Symmetric Cryptographic Intel FPGA Hard IP User Guide

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ID 714305
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Cryptographic IP Data Profiles 7. Configuration Registers 8. Design Example 9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives 10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
1. Introduction x
1.1. Terminology 1.2. IP Core Overview 1.3. Release Information 1.4. Device Family Support 1.5. Resource Utilization
1.2. IP Core Overview x
1.2.1. IP Core Applications
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. AXI-ST Interface 2.4. AXI-Lite Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Symmetric Cryptographic IP Core Flow 4.5. Dynamically Disabling SM4 Capability 4.6. Error Handling 4.7. Error Reporting 4.8. Resetting the IP Core 4.9. Channel Definition and Allocation 4.10. Byte Ordering 4.11. AXI-ST Single Packet Mode 4.12. AXI-ST Multiple Packet Mode
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.6. Error Handling x
4.6.1. Detected Error Handling 4.6.2. Key RAM ECC Error Handling
5. Block Description x
5.1. Reset Sequencer 5.2. AXI-ST Ready Latency 5.3. AXI Adapter 5.4. Integrity Check Value Comparison 5.5. GCM Padding and Depadding
5.3. AXI Adapter x
5.3.1. MAC Packing 5.3.2. Data Last Indicator 5.3.3. Stream and Channel ID Buffering 5.3.4. TKEEP and LAST_SEGMENT Signals Generation 5.3.5. MAC Dropping on Decryption
5.5. GCM Padding and Depadding x
5.5.1. GCM Padding 5.5.2. GCM Depadding
6. Cryptographic IP Data Profiles x
6.1. MAC Security Profile (MACsec) 6.2. IP Security Profile (IPsec) 6.3. Generic GCM Profile (GCM) 6.4. Generic XTS Profile (XTS)
6.1. MAC Security Profile (MACsec) x
6.1.1. MACsec Flow 6.1.2. AXI-ST Interface Using MAC Security (MACsec) Profile Pattern
6.2. IP Security Profile (IPsec) x
6.2.1. AXI-ST Interface Using IP Security (IPsec) Profile Pattern
6.3. Generic GCM Profile (GCM) x
6.3.1. AXI- ST Interface Using Generic GCM Profile Pattern
6.4. Generic XTS Profile (XTS) x
6.4.1. AXI-ST Interface Using Generic XTS Profile Pattern
8. Design Example x
8.1. Functional Description 8.2. Crypto VSIP Top Block Descriptions 8.3. Test Configurations 8.4. Software Requirements 8.5. Simulation Requirements 8.6. Steps to Generate the Design Example 8.7. Running Simulation Tests 8.8. Running Hardware Tests
8.2. Crypto VSIP Top Block Descriptions x
8.2.1. Clock and Reset 8.2.2. Host Interface
8.7. Running Simulation Tests x
8.7.1. Steps to Simulate the Design Example
8.8. Running Hardware Tests x
8.8.1. Supported Boards 8.8.2. Steps to Compile the Design Example for Hardware 8.8.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide

5. Block Description

The following block diagram shows the interconnections of Symmetric Cryptographic IP.
Figure 9. Block Diagram
AES and SM4 Inline Cryptographic Accelerator (AES and SM4 ICA): A hardened IP block that performs the data encryption or decryption. This IP block supports the following:
  • AES and SM4 cryptographic algorithms
  • 128 bit, 256 bit, or 512 bit key size, the key size depends on the specified mode. The 512 bit key includes the tweak and data for the AES XTS mode.
  • Single 512-bit data interface
  • MAC Security (MACsec), IP Security (IPsec), Galois/Counter mode (GCM), and XEX-based tweak-code block mode (XTS)-specific profiles. Each profile provides a unique set of cryptographic settings.
  • Interleaved data profiles (with the exception of MACSec and XTS profile interleaving).

Reset Sequencer: Resets the sequence within the Symmetric Cryptographic Intel FPGA Hard IP. The block interfaces with the central soft reset controller and the AES/SM4 Inline Cryptographic Accelerator. For more information, refer to Reset Sequencer.

AXI-ST Ready Latency: Available for AXI-ST ingress responder ports only, the AXI-ST ready latency supports 0 to 15 range and is compliant with the AXI specification. For more information, refer to AXI-ST Ready Latency.

AXI-ST Adapter: The adapter handles the AXI-ST interface adaptation and performs the packing and unpacking of the AXI-ST tuser bits into the data bus before the request is sent to the AES/SM4 Inline Cryptographic Accelerator.

ICV Comparison and MAC packing: The IP core generates an authentication tag and compares it with the authentication tag carried from the decryption process. For more information, refer to Integrity Check Value Comparison.


Section Content
Reset Sequencer
AXI-ST Ready Latency
AXI Adapter
Integrity Check Value Comparison
GCM Padding and Depadding

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