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1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores
4.2. Specifying the IP Core Parameters and Options
4.3. Generated File Structure
4.4. Symmetric Cryptographic IP Core Flow
4.5. Dynamically Disabling SM4 Capability
4.6. Error Handling
4.7. Error Reporting
4.8. Resetting the IP Core
4.9. Channel Definition and Allocation
4.10. Byte Ordering
4.11. AXI-ST Single Packet Mode
4.12. AXI-ST Multiple Packet Mode
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1.2. IP Core Overview
The Symmetric Cryptographic Intel FPGA IP consists of the Advanced Encryption Standard (AES) and SM4 Inline Cryptographic Accelerator (ICA) subsystems. Each device supports two identical IP subsystems, located at the north and the south of the device periphery. You can also instantiate the IP as a standalone cryptographic accelerator engine.
Features | Description |
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AES-GCM Mode |
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AES-XTS Mode |
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SM4 Algorithm |
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Interfaces |
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Performance |
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Certifications | NIST CAVP:
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Other features |
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