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1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores
4.2. Specifying the IP Core Parameters and Options
4.3. Generated File Structure
4.4. Symmetric Cryptographic IP Core Flow
4.5. Dynamically Disabling SM4 Capability
4.6. Error Handling
4.7. Error Reporting
4.8. Resetting the IP Core
4.9. Channel Definition and Allocation
4.10. Byte Ordering
4.11. AXI-ST Single Packet Mode
4.12. AXI-ST Multiple Packet Mode
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4.6.2. Key RAM ECC Error Handling
The IP core always reports the key RAM ECC error as an internal error, asserting the 0x4 error code.
The cause for this error depends on the specific settings. The below case describes the scenario when you preloaded the tweak value:
- When you send in a tweak value encrypted with the 2nd key (key 2), the IP returns a tweak value of 0. When the key RAM ECC error code (0x04) asserts and the internal error pin does not assert, the error is due to the encrypted tweak being calculated as a 0.
Note: When Key RAM ECC error code is masked, this error causes 0x00 error code assertion.
- A tweak value of 0 weakens the XTS mode. The IP flags this condition as an error. You may choose to ignore this error scenario by masking the 0x04 and 0x00 error codes.