Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/02/2023
Public
Document Table of Contents

2.2. Reset Signals

Table 9.  Reset Signals
Port Name Width (Bits) Domain Description
subsystem_cold_rst_n 1 Asynchronous Active low, hard global reset.

Resets the entire Symmetric Cryptographic IP core.

subsystem_cold_rst_ack_n 1 Asynchronous Active low, acknowledgment signal for the subsystem_cold_rst_n reset.

You must not deassert the subsystem_cold_rst_n reset signal until the

subsystem_cold_rst_ack_n is asserted.