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1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores
4.2. Specifying the IP Core Parameters and Options
4.3. Generated File Structure
4.4. Symmetric Cryptographic IP Core Flow
4.5. Dynamically Disabling SM4 Capability
4.6. Error Handling
4.7. Error Reporting
4.8. Resetting the IP Core
4.9. Channel Definition and Allocation
4.10. Byte Ordering
4.11. AXI-ST Single Packet Mode
4.12. AXI-ST Multiple Packet Mode
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8.6. Steps to Generate the Design Example
- Create a project with device OPN AGFD023R25A2E2VR0 or with another Intel® Agilex™ 7 device that includes the Symmetric Cryptographic Intel FPGA Hard IP.
- Open the Symmetric Cryptographic Intel FPGA Hard IP GUI.
- Click on the "Acknowledgement" button under the Example Design Options menu. This explicitly states that the example design is generated per the drop-down menu and doesn’t follow any other GUI parameters except for the device Ordering Part Number (OPN).
Figure 34. Example Design Options Menu
- Choose the appropriate Example Design.
Figure 35. Choosing Example Design
- Click on "Generate Example Design."