Symmetric Cryptographic Intel FPGA Hard IP User Guide

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ID 714305
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Cryptographic IP Data Profiles 7. Configuration Registers 8. Design Example 9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives 10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
1. Introduction x
1.1. Terminology 1.2. IP Core Overview 1.3. Release Information 1.4. Device Family Support 1.5. Resource Utilization
1.2. IP Core Overview x
1.2.1. IP Core Applications
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. AXI-ST Interface 2.4. AXI-Lite Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Symmetric Cryptographic IP Core Flow 4.5. Dynamically Disabling SM4 Capability 4.6. Error Handling 4.7. Error Reporting 4.8. Resetting the IP Core 4.9. Channel Definition and Allocation 4.10. Byte Ordering 4.11. AXI-ST Single Packet Mode 4.12. AXI-ST Multiple Packet Mode
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.6. Error Handling x
4.6.1. Detected Error Handling 4.6.2. Key RAM ECC Error Handling
5. Block Description x
5.1. Reset Sequencer 5.2. AXI-ST Ready Latency 5.3. AXI Adapter 5.4. Integrity Check Value Comparison 5.5. GCM Padding and Depadding
5.3. AXI Adapter x
5.3.1. MAC Packing 5.3.2. Data Last Indicator 5.3.3. Stream and Channel ID Buffering 5.3.4. TKEEP and LAST_SEGMENT Signals Generation 5.3.5. MAC Dropping on Decryption
5.5. GCM Padding and Depadding x
5.5.1. GCM Padding 5.5.2. GCM Depadding
6. Cryptographic IP Data Profiles x
6.1. MAC Security Profile (MACsec) 6.2. IP Security Profile (IPsec) 6.3. Generic GCM Profile (GCM) 6.4. Generic XTS Profile (XTS)
6.1. MAC Security Profile (MACsec) x
6.1.1. MACsec Flow 6.1.2. AXI-ST Interface Using MAC Security (MACsec) Profile Pattern
6.2. IP Security Profile (IPsec) x
6.2.1. AXI-ST Interface Using IP Security (IPsec) Profile Pattern
6.3. Generic GCM Profile (GCM) x
6.3.1. AXI- ST Interface Using Generic GCM Profile Pattern
6.4. Generic XTS Profile (XTS) x
6.4.1. AXI-ST Interface Using Generic XTS Profile Pattern
8. Design Example x
8.1. Functional Description 8.2. Crypto VSIP Top Block Descriptions 8.3. Test Configurations 8.4. Software Requirements 8.5. Simulation Requirements 8.6. Steps to Generate the Design Example 8.7. Running Simulation Tests 8.8. Running Hardware Tests
8.2. Crypto VSIP Top Block Descriptions x
8.2.1. Clock and Reset 8.2.2. Host Interface
8.7. Running Simulation Tests x
8.7.1. Steps to Simulate the Design Example
8.8. Running Hardware Tests x
8.8.1. Supported Boards 8.8.2. Steps to Compile the Design Example for Hardware 8.8.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide

4.7. Error Reporting

The Symmetric Cryptographic IP core can report various types of errors: ICV errors, client errors, AES/SM4 Inline Cryptographic Accelerator errors, bridge-specific errors, and any other fatal internal errors including a FIFO overflow errors.
The IP uses three mechanisms to report errors:
  1. tuser.err_code signal: Used for errors associated with a profile, channel, or data cycle.

    The error propagates out with the AXI-ST data cycle. The error is valid when AXI-ST valid signal is set to 1 and the tuser_error_status signal is set to 1. The signal can only forward a single error code in the event of multiple simultaneous errors. You can include or exclude errors through the static configuration registers, such as err_code_ctrl1, err_code_ctrl2, and err_code_int signals.

  2. tuser.internal_error signal: Used for errors that cannot be associated with a profile, channel, or data cycle. Also, used for errors that can leave the datapath unreliable.

    This signal asserts independently from the AXI-ST interface. The error is a pulse signal that is a bit-synchronized over to the fabric clock domain. You can include or exclude errors through the static pinerr_ctrl register.

  3. Error Status Logs via different types of files:
    • First Error Log (ferr_log): Monitors the internal errors and packet errors reported on AXI-ST datapath and captures the first error to assert. Each error can be included or excluded from this by setting the Static Configuration registers interr_ctrl, pacerr_ctrl1, pacerr_ctrl2.
    • Internal Error Log (interr_log): Contains the internal errors reported by various submodules within the datapath.
    • Packet Error Log 1 (pacerr_log1): Contains errors for generic GCM and generic XTS profiles.
    • Packet Error Log 2 (pacerr_log2): Contains errors for MACsec and IPsec profiles.

Bridge Clearing Mechanism

The IP supports the following clearing mechanisms:
Table 20.  Bridge Clearing Signals
Signal Name Description
subsystem_cold_reset_n Global reset
tuser.error_clear Profile-based in-band reset sent with tvalid signal and a profile ID. Clears the bridge specified by the profile ID.

This signal does not clear the AES/SM4 Inline Cryptographic Accelerator.

ctrl_primary.clear_macsec_bridge_states

ctrl_primary.clear_ipsec_bridge_states

ctrl_primary.clear_gcm_bridge_states

ctrl_primary.clear_xts_bridge_states

Profile-based resets used as a backup feature.

These signals do not clear the AES/SM4 Inline Cryptographic Accelerator.

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