Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/02/2023
Public
Document Table of Contents

10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.10.02 23.3 1.4.0 Updated the note in the MAC Security Profile (MACsec) section.
2023.04.03 23.1 1.4.0
  • Updated the Device Family Support table.
  • Updated the figure IP Parameter Editor in the Parameters chapter.
  • Incorporated the Allow key pre-programming for GCM profiles interleaving XTS option in the IP Parameter Settings table in the Parameters chapter.
  • Incorporated a link to the register map in the Configuration Registers chapter.
  • Updated product family name to Intel Agilex 7.
2022.12.19 22.4 1.3.0
  • Added certification features in the table Symmetric Cryptographic Intel FPGA IP Features.
  • Updated the figure: IP Parameter Editor.
  • Added 2 parameters to the table IP Parameter Settings.
  • Updated the Block Diagram in Chapter 5 (Block Description).
  • Added the section GCM Padding and Depadding and two sub-secitons (GCM Padding, GCM Depadding).
  • Made other miscellaneous text edits.
2022.10.31 22.3 1.2.0
  • Added descriptions of new terminologies.
  • Added description for Example of a Network Storage and Confidential Computing Application figure.
  • Added description for Example of a Hybrid Security Application figure.
  • Added Theoretical Throughput as a Function of pp_ip_st_clk Clock Frequency table.
  • Revised the Design Example chapter.
2022.06.20 22.2 1.1.1
  • Added that error_clear cycle should be an standalone transaction with the intended profile, stream, or channel and is not to be mixed with a key or a data cycle.
  • Updated the IP Parameter Editor figure in Parameters.
  • Removed support for EDA ModelSim simulator.
  • Updated cryptographic code errors in Error Handling.
  • Defeatured interleaving the MACsec and XTS profile.
2022.04.13 22.1 1.1.0 Initial release.