Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/02/2023
Public
Document Table of Contents

8.7.1. Steps to Simulate the Design Example

  1. Navigate to <design-example-directory>/example_design/testbench.
  2. Type appropriate command for your simulator:
    Simulator Command
    VCS sh run_vcs.sh
    VCSMX sh run_vcsmx.sh
    Questasim -c -do run_vsim.tcl
    Xcelium sh run_xcelium.sh
  3. Observe simulation output. The successful simulation displays a TEST PASSED message.

    The following sample output illustrates a successful simulation test run for the Symmetric Cryptographic IP core design example testbench:

    TX_through put =31891672308.733921 bps
    RX_through put =27731888964.116455 bps
    QHIP latency min = 0.000000ns
    QHIP latency max = 0.000000ns
    QHIP latency avg = 0.000000ns
    AUTH counters c0=0 c1=0 c2=0 c3=0
    packet count 80
    Dynamic IOPLL AXI-ST clock frequency count 0.000000 FREQUENCY = inf MHz
    Dynamic IOPLL Crypto clock frequency count 0.000000 FREQUENCY =inf MHz
    ***********************************************************************
    SOP0 count is 80
    EOP0 count is 80
    RX PT count is 40
    ************************************************************************
    ****** TEST PASSED *****************************************************