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1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores
4.2. Specifying the IP Core Parameters and Options
4.3. Generated File Structure
4.4. Symmetric Cryptographic IP Core Flow
4.5. Dynamically Disabling SM4 Capability
4.6. Error Handling
4.7. Error Reporting
4.8. Resetting the IP Core
4.9. Channel Definition and Allocation
4.10. Byte Ordering
4.11. AXI-ST Single Packet Mode
4.12. AXI-ST Multiple Packet Mode
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8.7.1. Steps to Simulate the Design Example
- Navigate to <design-example-directory>/example_design/testbench.
- Type appropriate command for your simulator:
Simulator Command VCS sh run_vcs.sh VCSMX sh run_vcsmx.sh Questasim -c -do run_vsim.tcl Xcelium sh run_xcelium.sh - Observe simulation output. The successful simulation displays a TEST PASSED message.
The following sample output illustrates a successful simulation test run for the Symmetric Cryptographic IP core design example testbench:
TX_through put =31891672308.733921 bps RX_through put =27731888964.116455 bps QHIP latency min = 0.000000ns QHIP latency max = 0.000000ns QHIP latency avg = 0.000000ns AUTH counters c0=0 c1=0 c2=0 c3=0 packet count 80 Dynamic IOPLL AXI-ST clock frequency count 0.000000 FREQUENCY = inf MHz Dynamic IOPLL Crypto clock frequency count 0.000000 FREQUENCY =inf MHz *********************************************************************** SOP0 count is 80 EOP0 count is 80 RX PT count is 40 ************************************************************************ ****** TEST PASSED *****************************************************