Intel® Stratix® 10 MX FPGA Development Kit User Guide

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ID 683867
Date 6/15/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Components Overview 4.2. Intel® MAX® 10 FPGA System Controller 4.3. Intel® MAX® 10 FPGA Power Manager 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Interfaces and Ports 4.7. HiLo Daughter Cards 4.8. Clocks 4.9. Power
4.6. Interfaces and Ports x
4.6.1. PCI Express 4.6.2. Memory Interface 4.6.3. High Bandwidth Memory (HBM2) 4.6.4. QSFP 4.6.5. I2C Flash Memory
4.6.2. Memory Interface x
4.6.2.1. On-board DDR4 Memory Interface 4.6.2.2. DDR4/DDR-T DIMM Memory Interface 4.6.2.3. HiLo Memory Interface
4.7. HiLo Daughter Cards x
4.7.1. DDR4 4.7.2. QDR-IV
4.9. Power x
4.9.1. Power Guidelines 4.9.2. Power Distribution System 4.9.3. Power Sequence 4.9.4. Power Measurement 4.9.5. Power Fast Discharging 4.9.6. Thermal Limitations and Protection 4.9.7. Cooling Design 4.9.8. Mechanical Information 4.9.9. Top Cover Removal
5. Board Test System x
5.1. Preparing the Board Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The Sys Info Tab 5.3.3. The QSFP Tab 5.3.4. The PCIE Tab 5.3.5. The Component DDR4 Tab 5.3.6. The HiLo DDR4 Tab 5.3.7. The DDR4 Dimm Tab 5.3.8. The HBM2 Top Tab 5.3.9. The HBM2 Bottom Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in the QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Statement
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
B. Revision History x
B.1. Revision History
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.6.4. QSFP

The Intel® Stratix® 10 MX FPGA development kit includes two Quad Small Form-Factor Pluggable (QSFP) connectors (J4, J5). Each connector is mapped to the FPGA’s 28 Gbps transceivers. There are four transceivers per connector supporting up to 100 Gbps data rate.

Table 17.  QSFP_1 (J5) Pin Connections
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard Description
28 ZQSFP1_3V3_INT_L A4 (MAX10 U24) 3.3V QSFP interrupt
31 ZQSFP1_3V3_LPMODE B6 (MAX10 U24) 3.3V QSFP low power mode
27 ZQSFP1_3V3_MODPRS_L A6 (MAX10 U24) 3.3V Module present
9 ZQSFP1_3V3_RESET_L A7 (MAX10 U24) 3.3V Module reset
8 ZQSFP1_3V3_MODSEL_L B5 (MAX10 U24) 3.3V Module select
11 ZQSFP_I2C_SCL BJ16 via U15 1.8v QSFP serial 2-wire clock
12 ZQSFP_I2C_SDA BD16 via U15 1.8v QSFP serial 2-wire data
18 ZQSFP1_RX0_N AL6 1.4V PCML QSFP receiver data
21 ZQSFP1_RX1_N AK8 1.4V PCML QSFP receiver data
15 ZQSFP1_RX2_N AH8 1.4V PCML QSFP receiver data
24 ZQSFP1_RX3_N AG6 1.4V PCML QSFP receiver data
17 ZQSFP1_RX0_P AL5 1.4V PCML QSFP receiver data
22 ZQSFP1_RX1_P AK7 1.4V PCML QSFP receiver data
14 ZQSFP1_RX2_P AH7 1.4V PCML QSFP receiver data
25 ZQSFP1_RX3_P AG5 1.4V PCML QSFP receiver data
37 ZQSFP1_TX0_N AM4 1.4V PCML QSFP transmitter data
2 ZQSFP1_TX1_N AL2 1.4V PCML QSFP transmitter data
34 ZQSFP1_TX2_N AJ2 1.4V PCML QSFP transmitter data
5 ZQSFP1_TX3_N AH4 1.4V PCML QSFP transmitter data
36 ZQSFP1_TX0_P AM3 1.4V PCML QSFP transmitter data
3 ZQSFP1_TX1_P AL1 1.4V PCML QSFP transmitter data
33 ZQSFP1_TX2_P AJ1 1.4V PCML QSFP transmitter data
6 ZQSFP1_TX3_P AH3 1.4V PCML QSFP transmitter data
Table 18.  QSFP_0 (J4) Pin Connections
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard Description
28 ZQSFP0_3V3_INT_L E8 (MAX10 U24) 3.3 V QSFP interrupt
31 ZQSFP0_3V3_LPMODE A11 (MAX10 U24) 3.3 V QSFP low power mode
27 ZQSFP0_3V3_MODPRS_L A10 (MAX10 U24) 3.3 V Module present
9 ZQSFP0_3V3_RESET_L B10 (MAX10 U24) 3.3 V Module reset
8 ZQSFP0_3V3_MODSEL_L A3 (MAX10 U24) 3.3 V Module select
11 ZQSFP_I2C_SCL BJ16 via U15 1.8 V QSFP serial 2-wire clock
12 ZQSFP_I2C_SDA BD16 via U15 1.8 V QSFP serial 2-wire data
18 ZQSFP0_RX0_N AM44 1.4V PCML QSFP receiver data
21 ZQSFP0_RX1_N AK44 1.4V PCML QSFP receiver data
15 ZQSFP0_RX2_N AF44 1.4V PCML QSFP receiver data
24 ZQSFP0_RX3_N AH44 1.4V PCML QSFP receiver data
17 ZQSFP0_RX0_P AM45 1.4V PCML QSFP receiver data
22 ZQSFP0_RX1_P AK45 1.4V PCML QSFP receiver data
14 ZQSFP0_RX2_P AF45 1.4V PCML QSFP receiver data
25 ZQSFP0_RX3_P AH45 1.4V PCML QSFP receiver data
37 ZQSFP0_TX0_N AN50 1.4V PCML QSFP transmitter data
2 ZQSFP0_TX1_N AL50 1.4V PCML QSFP transmitter data
34 ZQSFP0_TX2_N AG50 1.4V PCML QSFP transmitter data
5 ZQSFP0_TX3_N AJ50 1.4V PCML QSFP transmitter data
36 ZQSFP0_TX0_P AN51 1.4V PCML QSFP transmitter data
3 ZQSFP0_TX1_P AL51 1.4V PCML QSFP transmitter data
33 ZQSFP0_TX2_P AG51 1.4V PCML QSFP transmitter data
6 ZQSFP0_TX3_P AJ51 1.4V PCML QSFP transmitter data
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