4.1. Components Overview
Board Reference | Type | Description |
---|---|---|
Featured Devices | ||
U1 | FPGA | Intel® Stratix® 10 MX FPGA1
|
U11 | FPGA | Intel® MAX® 10 FPGA, 4K LEs, 169 FBGA (System) |
U27 | FPGA | Intel® MAX® 10, 16K LEs, 169 FBGA (Power) |
Configuration and Setup Elements | ||
J15 | On-board Intel® FPGA Download Cable II | Micro-USB 2.0 connector for programming and debugging the FPGA. |
SW2 | JTAG Bypass DIP Switch | Enable and disable devices in the JTAG chain. This switch is located on the back of the board. |
SW1 | I2C Bus Selection Switch | Enable or Disable the I2C Bus for Clock chip, 3.3 V VRM, Main I2C, and Intel® Stratix® 10 FPGA |
S10 | CPU reset push button | The default reset for the FPGA logic. |
S1 | PCIe PERST 0 push button | This push button connects to Intel® Stratix® 10 FPGA's NPERSTL0 pin. |
S11 | PCIe PERST 1 push button | This push button connects to Intel® Stratix® 10 FPGA's NPERSTR1 pin. |
S12 | Intel® MAX® 10 Reset Push Button | The default reset for the Intel® MAX® 10 FPGA System Controller |
Status Elements | ||
D14 | Configuration Done LED | Illuminates when FPGA configuration is completed |
D16 | CvP Done LED | Illuminates when CvP process is completed |
D4 | Power LED (Blue) | Illuminates when board is powered on. |
D5 | Temperature LED (Green) | Illuminates when an over temperature condition occurs for the FPGA device. Ensure that an adequate heatsink/fan is properly installed. |
D7, D8, D9, D10 | User-defined LEDs | Four green color user LEDs. Illuminate when driven low. |
Clock Circuits | ||
U17 | Intel® MAX® 10 Reference Clock | Si510 Crystal Oscillator provides reference clocks for Intel® MAX® 10 devices
Default Frequencies are:
|
U16 | Programmable Clock Generator | Si5341A Programmable Clock Generator by the clock control GUI
Default Frequencies are:
|
U18 | Programmable Clock Generator | Si5338A Programmable Clock Generator by the Clock Control GUI
Default Frequencies are:
|
U19 | Programmable Clock Generator | Si5338B Programmable Clock Generator by the Clock Control GUI
Default Frequencies are:
|
Transceiver Interfaces | ||
J6 | PCIe* x16 gold fingers | PCIe* TX/RX x16 interface from FPGA bank 1C, 1D, 1E |
J7 | PCIe* x16 Root Port Connector | PCIe* TX/RX x16 interface from FPGA bank 4C, 4D, 4E |
J4 | QSFP Connector | Four TX/RX channels from FPGA Bank 1F |
J5 | QSFP Connector | Four TX/RX channels from 4F from FPGA bank 4F |
General User Input/Output | ||
D7, D8, D9. D10 | User defined LEDs | Four green color user LEDs. Illuminates when driven low. |
Memory Devices | ||
J2 | HiLo Connector | One x72 memory interface supporting DDR3 (x72), DDR4 (x72), QDR-IV (x36) and RLDRAM3 (x36). This development kit includes one plugin modules (daughtercards) that use the HiLo connector: DDR4 memory (x72) 1333 MHz |
J1 | DDR4, DDR-T, DIMM Socket |
One X72 memory interface supporting DDR4 (x72) or DDR-T memory module.
|
U3, U4, U5, U6, U7 | On-board DDR4 memory | On-board DDR4 memory (x72) 1333 MHz |
Communication Ports | ||
J6 | PCI Express* x16 Edge Connector | Gold-plated edge fingers for up to x16 signaling in either Gen1, Gen2 or Gen3 mode. |
J7 | PCI Express* x16 Root Port Connector | Standard PCI Express* Gen3 x16 Connector for connecting PCIe* Endpoint card. |
J4 | QSFP interface | Provides four transceiver channels per port for a 100G QSFP module |
J5 | QSFP interface | Provides four transceiver channels per port for a 100G QSFP module |
J13 | Linear Tech VRM PMBus Port | Provides PMBus connection using dongle from Linear Tech. |
J12 | Enpirion VRM PMBus Port | Provides PMBus connection using dongle from Intel® Enpirion® |
J9 | External JTAG Port | This port allows the use of Intel® FPGA Download Cable II dongle to access the JTAG links on the board. Connection to this port automatically disable the internal Intel® FPGA Download Cable II JTAG. |
J15 | Micro-USB Connector | Embedded Intel® FPGA Download Cable II JTAG for programming the FPGA via a USB cable. |
Power Supply | ||
J6 | PCI Express* edge connector | Interfaces to a PCI Express root port such as an appropriate PC motherboard. |
J11 | DC Input Jack | Accepts a 12 V DC power supply when powering the board from the provided power brick for lab bench operation. When operating from the PCIe* slot, this input must also be connected to the 8-pin Aux PCIe* power connector provided by the PC system along with J11, or else the board does not power on. |
SW3 | Power Switch | Switch to power ON or OFF the board when supplied from the DC input jack. |