Intel® Stratix® 10 MX FPGA Development Kit User Guide

ID 683867
Date 6/15/2020
Public
Document Table of Contents

4.8. Clocks

Figure 14.  Intel® Stratix® 10 MX FPGA Development Kit Clock Inputs and Default Frequencies
Table 27.  On-board Clocks
Source Schematic Signal Name Default Frequency I/O Standard Intel® Stratix® 10 FPGA Pin Number Application
U16 REFCLK_ZQSFP0_P 644.53125 MHz LVDS AJ43 QSFP0 Reference Clock
REFCLK_ZQSFP0_N 644.53125 MHz LVDS AJ42
REFCLK_ZQSFP1_P 644.53125 MHz LVDS AJ9 QSFP1 Reference Clock
REFCLK_ZQSFP1_N 644.53125 MHz LVDS AJ10
CLK_UIB0_P 100 MHz LVDS AR26 UIB0 Reference Clock
CLK_UIB0_N 100 MHz LVDS AP26
CLK_UIB1_P 100 MHz LVDS P27 UIB1 Reference Clock
CLK_UIB1_N 100 MHz LVDS R27
CLK_ESRAM0_P 100 MHz LVDS AU31 ESRAM0 Reference Clock
CLK_ESRAM0_N 100 MHz LVDS AU32
CLK_ESRAM1_P 100 MHz LVDS V31 ESRAM1 Reference Clock
CLK_ESRAM1_N 100 MHz LVDS U31
CLK_SYS_100M_P 100 MHz LVDS AU17 System Clock
CLK_SYS_100M_N 100 MHz LVDS AU16
REFCLK_PCIE_RT_P 100 MHz LVDS AW9 PCIe* Root Port Reference Clock
REFCLK_PCIE_RT_N 100 MHz LVDS AW10
REFCLK_PCIE_EP_P 100 MHz LVDS AW43 PCIe* End Point Reference Clock
REFCLK_PCIE_EP_N 100 MHz LVDS AW42
U18 CLK_SYS_50M_P 50 MHz LVDS BE17 FPGA Clocks
CLK_SYS_50M_N 50 MHz LVDS BD17
CLK_CORE_BAK_P 100 MHz LVDS AT13 FPGA Core Clocks
CLK_CORE_BAK_N 100 MHz LVDS AU13
S10_OSC_CLK_1 125 MHz LVCMOS AR35 Configuration Clock
REFCLK_PCIE_EP1_N 100 MHz LVDS BA42 PCIe* Transceivers Clock
REFCLK_PCIE_EP1_P 100 MHz LVDS BA43
U19 CLK_HILO_MEM_N 133.333 MHz LVDS AY31 HiLo Memory Clocks
CLK_HILO_MEM_P 133.333 MHz LVDS AW31
CLK_DDR4_COMP_N 133.333 MHz LVDS B41 On-board DDR4 Memory clocks
CLK_DDR4_COMP_P 133.333 MHz LVDS A42
CLK_DDR4_DIMM_N 133.333 MHz LVDS C18 DIMM Module Clocks
CLK_DDR4_DIMM_P 133.333 MHz LVDS B18