Intel® Stratix® 10 MX FPGA Development Kit User Guide

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ID 683867
Date 6/15/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Components Overview 4.2. Intel® MAX® 10 FPGA System Controller 4.3. Intel® MAX® 10 FPGA Power Manager 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Interfaces and Ports 4.7. HiLo Daughter Cards 4.8. Clocks 4.9. Power
4.6. Interfaces and Ports x
4.6.1. PCI Express 4.6.2. Memory Interface 4.6.3. High Bandwidth Memory (HBM2) 4.6.4. QSFP 4.6.5. I2C Flash Memory
4.6.2. Memory Interface x
4.6.2.1. On-board DDR4 Memory Interface 4.6.2.2. DDR4/DDR-T DIMM Memory Interface 4.6.2.3. HiLo Memory Interface
4.7. HiLo Daughter Cards x
4.7.1. DDR4 4.7.2. QDR-IV
4.9. Power x
4.9.1. Power Guidelines 4.9.2. Power Distribution System 4.9.3. Power Sequence 4.9.4. Power Measurement 4.9.5. Power Fast Discharging 4.9.6. Thermal Limitations and Protection 4.9.7. Cooling Design 4.9.8. Mechanical Information 4.9.9. Top Cover Removal
5. Board Test System x
5.1. Preparing the Board Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The Sys Info Tab 5.3.3. The QSFP Tab 5.3.4. The PCIE Tab 5.3.5. The Component DDR4 Tab 5.3.6. The HiLo DDR4 Tab 5.3.7. The DDR4 Dimm Tab 5.3.8. The HBM2 Top Tab 5.3.9. The HBM2 Bottom Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in the QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Statement
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
B. Revision History x
B.1. Revision History
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.4. FPGA Configuration

You can use the Intel® Quartus® Prime Programmer to configure the FPGA with your SRAM Object File (.sof).

Ensure the following

  • The Intel® Quartus® Prime Programmer is installed on your PC.
  • The micro-USB cable is connected to the FPGA development board.
  • Power to the board is ON, and no other applications that use the JTAG chain are running.

Steps

  1. Start the Intel® Quartus® Prime Programmer.
  2. Click Auto Detect to display the devices in the JTAG chain.
  3. Click Change File and select the path to the desired .sof.
  4. Turn on the Program/Configure option for the added file.
  5. Click Start to download the selected file to the FPGA. Configuration is complete when the progress bar reaches 100%.

Using the Intel® Quartus® Prime Programmer to configure a device on the board causes other JTAG based applications such as the Board Test System and the Power Monitor to lose their connection to the board. Restart those applications after configuration is complete.

Programming the FPGA over Intel® FPGA Download Cable II

The figure below shows the high-level conceptual block diagram for programming the Intel® Stratix® 10 MX FPGA over the embedded Intel® FPGA Download Cable II or External Intel® FPGA Download Cable II.

Figure 7. Embedded Intel® FPGA Download Cable Conceptual Block Diagram

Connection on the external JTAG header (J9) automatically disables the on-board JTAG Intel® FPGA Download Cable II. This allows the use of an external USB JTAG dongle to access the JTAG bus on the board.

Supported Configuration Modes

This development kit supports two configuration modes: Active Serial x4 (AS x4) and JTAG. The default configuration is AS x4 using a 2 Gb QSPI Flash device. JTAG configuration is supported by using either the on-board Intel® FPGA Download Cable II or the through an external Intel® FPGA Download Cable II dongle.

Active Serial x4 Mode

The Secure Device Manager (SDM) block in the Intel® Stratix® 10 MX FPGA device controls the configuration process and interface. The flash memory is a Micron Technology 1.8 V core, 1.8 V I/O 2 Gigabit CFI NOR-type device (P/N: MT25Qu02GCBB3E12). For AS x4 Fast modes, MSEL [2:0] signals need to be set according to the table below. Not all modes are supported. AS x4 is the default configuration mode.

Table 8.  Active Serial Mode
Configuration Scheme MSEL [2:0]
Avalon-ST (x32) 000 (Not Supported)
Avalon-ST (x16) 101 (Not Supported)
Avalon-ST (x8) 110 (Not Supported)
AS (Fast Mode for CvP) 001
AS (Normal Mode) 011 (Not Supported)
NAND x8 010 (Not Supported)
SD/MMC x4/x8 100 (Not Supported)
JTAG only 111
Figure 8. AS x4 Configuration Conceptual Block Diagram

JTAG Configuration Mode

The JTAG Switch implemented in the Intel® MAX® 10 System Control FPGA (U24) allows the selection of the device(s) to be included in the JTAG chain. It is done by the settings of the DIP switch SW2. The embedded Intel® FPGA Download Cable (or external Intel® FPGA Download Cable) or PCIe* JTAG can be selected as the source for programming the device(s) on the chain. The embedded Intel® FPGA Download Cable is the default setting for this configuration mode.

Figure 9. JTAG Chain Conceptual Block Diagram
Note: AS x4 is default configuration mode. Changing to JTAG mode requires changing pull-up/pull-down resistors for the MSEL lines on the board. Please refer to the board schematics and layout for detailed resistor locations.
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