Intel® Stratix® 10 MX FPGA Development Kit User Guide

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ID 683867
Date 6/15/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Components Overview 4.2. Intel® MAX® 10 FPGA System Controller 4.3. Intel® MAX® 10 FPGA Power Manager 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Interfaces and Ports 4.7. HiLo Daughter Cards 4.8. Clocks 4.9. Power
4.6. Interfaces and Ports x
4.6.1. PCI Express 4.6.2. Memory Interface 4.6.3. High Bandwidth Memory (HBM2) 4.6.4. QSFP 4.6.5. I2C Flash Memory
4.6.2. Memory Interface x
4.6.2.1. On-board DDR4 Memory Interface 4.6.2.2. DDR4/DDR-T DIMM Memory Interface 4.6.2.3. HiLo Memory Interface
4.7. HiLo Daughter Cards x
4.7.1. DDR4 4.7.2. QDR-IV
4.9. Power x
4.9.1. Power Guidelines 4.9.2. Power Distribution System 4.9.3. Power Sequence 4.9.4. Power Measurement 4.9.5. Power Fast Discharging 4.9.6. Thermal Limitations and Protection 4.9.7. Cooling Design 4.9.8. Mechanical Information 4.9.9. Top Cover Removal
5. Board Test System x
5.1. Preparing the Board Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The Sys Info Tab 5.3.3. The QSFP Tab 5.3.4. The PCIE Tab 5.3.5. The Component DDR4 Tab 5.3.6. The HiLo DDR4 Tab 5.3.7. The DDR4 Dimm Tab 5.3.8. The HBM2 Top Tab 5.3.9. The HBM2 Bottom Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in the QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Statement
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
B. Revision History x
B.1. Revision History
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.6.2.3. HiLo Memory Interface

The HiLo Memory interface is mapped to the FPGA’s 2A, 2B and 2C I/O blocks. The connector supports plugins for the following memory interfaces:
  • DDR4 x72
  • QDR-IV x72
Table 16.  HiLo Memory Interface Pin Connections
Board Reference - HiLo Connector Pin Number Schematic Signal Name FPGA Pin Number I/O Standard
F1 MEM_ADDR_CMD0 BL34 Adjustable
H1 MEM_ADDR_CMD1 BK34 Adjustable
F2 MEM_ADDR_CMD2 BJ34 Adjustable
G2 MEM_ADDR_CMD3 BH34 Adjustable
H2 MEM_ADDR_CMD4 BH33 Adjustable
J2 MEM_ADDR_CMD5 BJ33 Adjustable
K2 MEM_ADDR_CMD6 BK35 Adjustable
G3 MEM_ADDR_CMD7 BL34 Adjustable
J3 MEM_ADDR_CMD8 BD33 Adjustable
L3 MEM_ADDR_CMD9 BC33 Adjustable
E4 MEM_ADDR_CMD10 BG33 Adjustable
F4 MEM_ADDR_CMD11 BF33 Adjustable
G4 MEM_ADDR_CMD12 BB33 Adjustable
H4 MEM_ADDR_CMD13 BB32 Adjustable
J4 MEM_ADDR_CMD14 BA32 Adjustable
K4 MEM_ADDR_CMD15 Aw32 Adjustable
M1 MEM_ADDR_CMD16 BF32 Adjustable
M2 MEM_ADDR_CMD17 BE32 Adjustable
N2 MEM_ADDR_CMD18 BD32 Adjustable
L4 MEM_ADDR_CMD19 BG32 Adjustable
P5 MEM_ADDR_CMD20 BD34 Adjustable
M5 MEM_ADDR_CMD21 BC34 Adjustable
P1 MEM_ADDR_CMD22 Aw34 Adjustable
R4 MEM_ADDR_CMD23 AV34 Adjustable
M4 MEM_ADDR_CMD24 BA34 Adjustable
R3 MEM_ADDR_CMD25 AY34 Adjustable
L2 MEM_ADDR_CMD26 AY32 Adjustable
K1 MEM_ADDR_CMD27 AW33 Adjustable
P2 MEM_ADDR_CMD28 AV33 Adjustable
N4 MEM_ADDR_CMD29 BL32 Adjustable
P4 MEM_ADDR_CMD30 BG35 Adjustable
N3 MEM_ADDR_CMD31 BH35 Adjustable
V2 MEM_CLK_P BF34 Adjustable
V1 MEM_CLK_N BE34 Adjustable
B10 MEM_DMA0 BF40 Adjustable
C4 MEM_DMA1 BD38 Adjustable
B17 MEM_DMA2 BE37 Adjustable
F17 MEM_DMA3 BH36 Adjustable
A4 MEM_DQA0 BJ39 Adjustable
B4 MEM_DQA1 BH40 Adjustable
B5 MEM_DQA2 BH39 Adjustable
B6 MEM_DQA3 BG40 Adjustable
A8 MEM_DQA4 BK40 Adjustable
B8 MEM_DQA5 BL40 Adjustable
B9 MEM_DQA6 BE40 Adjustable
A10 MEM_DQA7 BE39 Adjustable
B1 MEM_DQA8 BL38 Adjustable
B2 MEM_DQA9 BG38 Adjustable
C2 MEM_DQA10 BF38 Adjustable
C3 MEM_DQA11 BD39 Adjustable
E3 MEM_DQA12 BC38 Adjustable
D4 MEM_DQA13 BC39 Adjustable
D1 MEM_DQA14 BJ37 Adjustable
D2 MEM_DQA15 BL37 Adjustable
A12 MEM_DQA16 BD37 Adjustable
B12 MEM_DQA17 BF37 Adjustable
B13 MEM_DQA18 BG37 Adjustable
B14 MEM_DQA19 BB36 Adjustable
C15 MEM_DQA20 BC36 Adjustable
A16 MEM_DQA21 AW37 Adjustable
B16 MEM_DQA22 AY37 Adjustable
A18 MEM_DQA23 AW36 Adjustable
C16 MEM_DQA24 BA35 Adjustable
D16 MEM_DQA25 BB35 Adjustable
E16 MEM_DQA26 BC35 Adjustable
F16 MEM_DQA27 BF35 Adjustable
D17 MEM_DQA28 AY35 Adjustable
C18 MEM_DQA29 BD36 Adjustable
D18 MEM_DQA30 BE36 Adjustable
E18 MEM_DQA31 BE35 Adjustable
E2 MEM_DQA32 BK37 Adjustable
G16 MEM_DQA33 BG36 Adjustable
A6 MEM_DQSA_P0 BK39 Adjustable
A7 MEM_DQSA_N0 BL39 Adjustable
A2 MEM_DQSA_P1 BH38 Adjustable
A3 MEM_DQSA_N1 BJ38 Adjustable
A14 MEM_DQSA_P2 BA37 Adjustable
A15 MEM_DQSA_N2 BB37 Adjustable
F18 MEM_DQSA_P3 BJ36 Adjustable
G18 MEM_DQSA_N3 BK36 Adjustable
A11 MEM_QKA_P0 BF39 Adjustable
B18 MEN_QKA_P1 AY36 Adjustable
R6 MEM_DQ_ADDR_CMD0 BE31 Adjustable
T1 MEM_DQ_ADDR_CMD1 BG31 Adjustable
R2 MEM_DQ_ADDR_CMD2 BD31 Adjustable
T2 MEM_DQ_ADDR_CMD3 BB31 Adjustable
U2 MEM_DQ_ADDR_CMD4 BC31 Adjustable
U3 MEM_DQ_ADDR_CMD5 BH31 Adjustable
T4 MEM_DQ_ADDR_CMD6 BK32 Adjustable
U4 MEM_DQ_ADDR_CMD7 BJ32 Adjustable
T5 MEM_DQ_ADDR_CMD8 BL33 Adjustable
V4 MEM_DQ_ADDR_CMD_P BK31 Adjustable
V5 MEM_DQ_ADDR_CMD_N BJ31 Adjustable
V1 MEM_CLK_P BF34 Adjustable
V2 MEM_CLK_N BE34 Adjustable
M16 MEM_DMB0 BL24 Adjustable
U16 MEM_DMB1 BD28 Adjustable
U11 MEM_DMB2 BL30 Adjustable
U6 MEM_DMB3 BE30 Adjustable
H16 MEM_DQB0 BE27 Adjustable
J16 MEM_DQB1 BJ26 Adjustable
K16 MEM_DQB2 BK24 Adjustable
L16 MEM_DQB3 BF27 Adjustable
H17 MEM_DQB4 BH26 Adjustable
K17 MEM_DQB5 BL25 Adjustable
K18 MEM_DQB6 BJ24 Adjustable
L18 MEM_DQB7 BG27 Adjustable
M17 MEM_DQB8 BF28 Adjustable
N18 MEM_DQB9 BG28 Adjustable
P17 MEM_DQB10 Bk27 Adjustable
P18 MEM_DQB11 BJ27 Adjustable
R18 MEM_DQB12 BC28 Adjustable
T16 MEM_DQB13 BL27 Adjustable
T17 MEM_DQB14 BB28 Adjustable
T18 MEM_DQB15 BD27 Adjustable
U15 MEM_DQB16 BH29 Adjustable
T14 MEM_DQB17 BA29 Adjustable
U14 MEM_DQB18 BA28 Adjustable
V14 MEM_DQB19 BJ29 Adjustable
T13 MEM_DQB20 BK30 Adjustable
T12 MEM_DQB21 BC29 Adjustable
U12 MEM_DQB22 BD29 Adjustable
V12 MEM_DQB23 BL29 Adjustable
T10 MEM_DQB24 AV30 Adjustable
U10 MEM_DQB25 AY29 Adjustable
V10 MEM_DQB26 BA30 Adjustable
T9 MEM_DQB27 AW29 Adjustable
T8 MEM_DQB28 AV29 Adjustable
U8 MEM_DQB29 AY30 Adjustable
U7 MEM_DQB30 BH30 Adjustable
V6 MEM_DQB31 BG30 Adjustable
R16 MEM_DQB32 BL28 Adjustable
T6 MEM_DQB33 BF30 Adjustable
H18 MEM_DQSB_P0 BK26 Adjustable
J18 MEM_DQSB_N0 BK25 Adjustable
U18 MEM_DQSB_P1 BJ28 Adjustable
V18 MEM_DQSB_N1 BH28 Adjustable
V16 MEM_DQSB_P2 BF29 Adjustable
V17 MEM_DQSB_N2 BE29 Adjustable
V8 MEM_DQSB_P3 BB30 Adjustable
V9 MEM_DQSB_N3 BC30 Adjustable
M18 MEM_QKB_P0 BG26 Adjustable
V13 MEM_QKB_P1 BK29 Adjustable
Level Two Title